ECEU530 Project Presentations ECE U530 Wednesday November 15: - - PDF document

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ECEU530 Project Presentations ECE U530 Wednesday November 15: - - PDF document

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ECEU530 Project Presentations ECE U530 Wednesday November 15: Digital Hardware Synthesis Corey, Rishi, Oshin, John, Daryl, Natalie Monday, November 20: Prof. Miriam Leeser Shuba, Paul, Doug, Shao-Han, Samir mel@coe.neu.edu

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SLIDE 1

ECEU530

ECE U530 Digital Hardware Synthesis

  • Lecture 18:
  • Student project presentations
  • Memories and FPGAs
  • Tri-state buffers and busses
  • Student project presentations:
  • Wednesday, Nov 15 and Monday, November 20

ECE U530 F06

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  • Prof. Miriam Leeser

mel@coe.neu.edu November 15, 2006

ECE U530 F’06 2

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Project Presentations

  • Wednesday November 15:

–Corey, Rishi, Oshin, John, Daryl, Natalie

  • Monday, November 20:

–Shuba, Paul, Doug, Shao-Han, Samir

  • You should give a 5 minute presentation about your

project in class:

  • What is your project
  • What are the challenges
  • What have you accomplished so far?

ECE U530 F’06 3

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Rest of Semester

  • Upcoming lectures:
  • Pipelining
  • Designing a complex multiply accumulator:

– Chapter 6 of Ashenden

  • Quiz in class on December 4
  • Sign up to demo your working project code to me

November 20th or 21st

  • Project due dates:
  • Nov 20: Preliminary Project Report
  • Your report should include:
  • A description of your project and what it does
  • VHDL code -- should be commented
  • Simulation results
  • Plan for the rest of the semester
  • Dec 13: Final Project Report Due at noon!

ECE U530 F’06 4

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Memory Structures

  • Register
  • Register File
  • ROM: Read only memory
  • RAM: Random access memory
  • Embedded RAM in FPGAs: Select RAM
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SLIDE 2

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Memory Block Diagram

  • A basic memory system is shown

here:

  • k address lines are decoded to

address 2k words of memory

  • Each word is m bits
  • Read and Write are single bit

control lines defining the simple memory operations m Data Input Lines k Address Lines Read Write m Data Output Lines Memory Unit 2k Words m Bits per Word k 1 1 m m

ECE U530 F’06 6

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Basic Memory Operations

  • Read Memory Read a data value stored in memory:
  • Place a valid address on the address lines
  • Wait for the read data to become stable
  • Write Memory Write a data value to memory:
  • Place a valid address on the address lines and valid data on

the data lines

  • Toggle the memory write control line
  • Sometimes the read or write enable line is defined as a

clock with precise timing information (e.g. Read Clock, Write Strobe).

  • Otherwise, it is just an interface signal
  • Sometimes memory must acknowledge that it has completed

the operation -- handshaking

ECE U530 F’06 7

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Generic RAM (1)

LIBRARY ieee; USE ieee.std_logic_1164.all;

  • ENTITY ram IS

GENERIC (bits: INTEGER := 8; -- # of bits per word words: INTEGER := 16); -- # of words in the memory PORT ( wr_ena, clk: IN STD_LOGIC; addr: IN INTEGER RANGE 0 to words – 1; data_in: IN STD_LOGIC_VECTOR(bits – 1 downto 0); data_out: OUT STD_LOGIC_VECTOR(bits – 1 downto 0) ); END ram;

ECE U530 F’06 8

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Generic RAM (2)

ARCHITECTURE behavioral OF ram IS TYPE vector_array IS ARRAY (0 TO words-1) OF STD_LOGIC_VECTOR(bits – 1 DOWNTO 0); SIGNAL memory: vector_array; BEGIN PROCESS(clk, wr_ena) BEGIN IF(wr_ena=‘1’) THEN IF (clk’EVENT AND clk=‘1’) THEN memory(addr) <= data_in; END_IF; END IF; END PROCESS; data_out <= memory(addr); END ram;

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SLIDE 3

ECEU530

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Microprocessor Register File

  • For read operations,

functionally the regfile is equivalent to a 2-D array of flip-flops with tristate outputs

  • n each
  • MUX, but distributed
  • Unary control
  • Cell with added write logic:

These circuits are just functional abstractions of the actual circuits used.

ECE U530 F’06 10

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Multi-ported Memory

  • Motivation:
  • Consider CPU core register file:

– 1 read or write per cycle limits processor performance. – Complicates pipelining. Difficult for different instructions to simultaneously read or write regfile. – Common arrangement in pipelined CPUs is 2 read ports and 1 write port – 2 read ports: dual ported memory sela selb selc dataa datab datac Regfile

ECE U530 F’06 11

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Behavioral Description of a Register File

library IEEE; use IEEE.std_logic_1164.all; use IEEE.std_logic_arith.all; entity regfile is port(write_data: in std_logic_vector(31 downto 0); dst_addr,src1_addr,src2_addr: in UNSIGNED(4 downto 0); write_cntrl: in std_logic; src1_data,src2_data: out std_logic_vector(31 downto 0)); end regfile;

Register File src1_addr src2_addr dst_addr write_data 32 bits src1_data src2_data 32 words write_cntrl

ECE U530 F’06 12

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Behavioral Description of a Register File, asynchronous

architecture process_behavior of regfile is type reg_array is array(0 to 31) of std_logic_vector (31 downto 0); begin regfile_process: process(src1_addr,src2_addr,dst_addr,write_cntrl) variable data_array: reg_array := ( (X”00000000”), (X”00000000”), . . . (X”00000000”)); variable addrofsrc1, addrofsrc2, addrofdst: integer; begin addrofsrc1 := conv_integer(src1_addr); addrofsrc2 := conv_integer(src2_addr); addrofdst := conv_integer(dst_addr); if write_cntrl = ‘1’ then data_array(addrofdst) := write_data; end if; src1_data <= data_array(addrofsrc1) after 10 ns; src2_data <= data_array(addrofsrc2) after 10 ns; end process regfile_process; end process_behavior;

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SLIDE 4

ECEU530

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Xilinx FPGA Architecture

  • CLB

Configurable Logic Block IOB Input/Output Block PSM Programmable Switch Matrix PIP Programmable Interconnect Point

ECE U530 F’06 14

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Using SRAM to Implement Logic

ECE U530 F’06 15

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A Simplified Logic Slice

ECE U530 F’06 16

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Mapping a Function to a 4-input LUT

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SLIDE 5

ECEU530

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CLB Used as RAM

ECE U530 F’06 18

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Memory Blocks in FPGAs

  • LUTs can double as small RAM blocks:
  • 4-LUT is really a 16x1 memory. Normally

we think of the contents being written from the configuration bit stream, but Virtex architecture (and others) allow bits of LUT to be written and read from the general interconnect structure.

  • achieves 16x density advantage over using

CLB flip-flops.

  • Furthermore, the two LUTs within a slice

can be combined to create a 16 x 2-bit or 32 x 1-bit synchronous RAM, or a 16x1-bit dual-port synchronous RAM.

  • The Virtex-E LUT can also provide a 16-bit

shift register of adjustable length.

  • Newer FPGA families include larger on-

chip RAM blocks (usually dual ported):

  • Called block selectRAMs in Xilinx Virtex

series

  • 4k bits each

ECE U530 F’06 19

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RAM16X1S

O D WE WCLK A0 A1 A2 A3

RAM32X1S

O D WE WCLK A0 A1 A2 A3 A4

RAM16X2S

O1 D0 WE WCLK A0 A1 A2 A3 D1 O0

= =

LUT LUT

  • r

LUT

RAM16X1D

SPO D WE WCLK A0 A1 A2 A3 DPRA0 DPO DPRA1 DPRA2 DPRA3

  • r

Distributed RAM

  • CLB LUT configurable as Distributed

RAM

  • A LUT equals 16x1 RAM
  • Implements Single and Dual-Ports
  • Cascade LUTs to increase RAM size
  • Synchronous write
  • Synchronous/Asynchronous read
  • Accompanying flip-flops used for

synchronous read

ECE U530 F’06 20

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DSP Coefficients Small FIFOs Scratch Pad

16x1

Distributed RAM

  • Single-port
  • Dual port
  • Cascadable

Cache Tag memory Large FIFOs Packet buffers Video line buffers

Block RAMs

  • 4Kbit blocks
  • True dual-port

SDRAM SGRAM PB SRAM DDR SRAM ZBT SRAM QDR SRAM

High-Performance External Memory Interfaces

  • DDR I/O
  • SSTL, HSTL, CTT

Spartan-IIE Memory Hierarchy

D CL K A3 A2 A1 A0 Q

SRL16

D CL K A3 A2 A1 A0 Q

SRL16E

C E

Shift Register LUT

  • 16 registers, 1 LUT
  • Compact & fast

Pipelining Buffers

Block RAM

4Kx1 2Kx2 1Kx4 512x8 256x16

Port A Port B

Collaboration with memory vendors IDT, Cypress, Micron, NEC, Samsung, Toshiba...

Bytes Kilobytes Megabytes

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SLIDE 6

ECEU530

ECE U530 F’06 21

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FPGA Embedded Memory Summary

  • Fast distributed RAM
  • Data right beside logic
  • Memory requirements solved by Block RAM
  • Single and True Dual-Port RAM implementations
  • FIFO for buffering data
  • Data width conversion
  • Cache
  • Register stacks
  • CAM for high-speed parallel searches
  • Many more
  • Direct connection to external high-speed memory

ECE U530 F’06 22

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Memories in VHDL for Xilinx

  • Look at the Language Templates in Project Manager

for how to describe memories in VHDL for FPGAs

  • Synthesis Templates:
  • Distributed RAM
  • Block RAM
  • Component Instantiations

ECE U530 F’06 23

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Tri-State Buffers

  • The input signal is only connected to the output signal when the

enable signal is asserted

  • Tri state buffers are used when multiple gates may need to drive

a single logical signal line

  • Care must be taken to ensure that only one output is enabled to

drive the output signal at any given time

ENABLE IN OUT

1 1 1 1 Z Z 1 Out E In

ECE U530 F’06 24

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Using tri-state buffers

E0 I0 E1 I1 E2 I2 OUT

Tri-state buffers are like a distributed mux 1 1 1 1 Z Z 1 Out E In

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SLIDE 7

ECEU530

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Registers Connected by a Tri-state Bus

  • Can make any register transfer R[i]←

← ← ←R[j]

  • Can’t have Gi = Gj = 1 for ij
  • Violating this constraint gives low resistance path from

power supply to ground