ECEU530 ECE U530 Digital Hardware Synthesis Prof. Miriam Leeser mel@coe.neu.edu Sept 13, 2006 • Lecture 3: Basic VHDL constructs • Signals, Variables, Constants • VHDL Simulator and Test benches • Types • Reading: Ashenden 2.1, 2.2, 5.1, 5.2 • Complete tutorial by Monday Sept 18 • Quiz in class on Monday, Sept 25 • based on tutorial lect03.ppt ECE U530 F06 Course Accounts and Tools • You must have a COE account for this course • Programming assignments will be done on WinCOE systems on second floor of Snell Engineering or 9 Hayden labs • Tools: Xilinx ISE version 6.2i, Modelsim 5.7e • If you are registered for this class, A sub-directory called Courses/ECEU530 will automatically appear in your home directory • IMPORTANT: Do NOT create this directory ! • Do not use this as your active working directory ! • only files submitted for homework should be in this directory • use your home directory (Z:) for all design work ! • tutorial should be done in your home directory lect03.ppt 2 ECE U530 F’06
ECEU530 Xilinx and Modelsim Tutorial • Create a directory for this course in your COE home directory: • Open an Explorer window (right click on Start and choose Explore) • Navigate to Coewin � � winusers � � User_Name � � � � This is your directory on the COE system • Create a new folder called 530local : right click in the directory and choose New � � Folder � � • (You may already have a folder called ECEU530) • Note: It is important that you not put empty spaces in any directory in the path for this course. The software tools do not recognize empty spaces. All names must be 8 characters or less. lect03.ppt ECE U530 F’06 3 For Help with Tools • For help with Xilinx or Modelsim: • send an email to mel@coe.neu.edu • Tell me, as specifically as possible: • what the problem is • what machine you are running on and where • Is it a problem in Modelsim or Xilinx ... • For help with login, coe account,etc. send email to: • help@coe.neu.edu lect03.ppt 4 ECE U530 F’06
ECEU530 lect03.ppt ECE U530 F’06 5 lect03.ppt 6 ECE U530 F’06
ECEU530 lect03.ppt ECE U530 F’06 7 Design Processing • Analysis • Elaboration • Simulation • Synthesis lect03.ppt 8 ECE U530 F’06
ECEU530 Analysis • Check for syntax and semantic errors • syntax: grammar of the language • semantics: the meaning of the model • Analyze each design unit separately • entity declaration • architecture body • … • Analyzed design units are placed in a library in an implementation dependent internal form • current library is called work lect03.ppt ECE U530 F’06 9 Elaboration • “Flattening” the design hierarchy • create ports • create signals and processes within architecture body • for each component instance, copy instantiated entity and architecture body • repeat recursively • bottom out at purely behavioral architecture bodies • Final result of elaboration • flat collection of signal nets and processes lect03.ppt 10 ECE U530 F’06
ECEU530 Elaboration Example bit0 reg4(struct) d_latch d0 q0 d q clk bit1 d_latch d1 q1 d q clk bit2 d_latch d2 q2 d q clk bit3 d_latch d3 q3 d q clk gate and2 en int_clk a y clk b lect03.ppt ECE U530 F’06 11 Elaboration Example bit0 reg4(struct) d_latch(basic) d0 q0 d q clk bit1 d_latch(basic) d1 q1 d q clk bit2 d_latch(basic) d2 q2 d q clk bit3 d_latch(basic) d3 q3 d q clk gate and2(basic) en int_clk a y process with variables clk b and statements lect03.ppt 12 ECE U530 F’06
ECEU530 Simulation • Execution of the processes in the elaborated model • Discrete event simulation • time advances in discrete steps • when signal values change— events • A processes is sensitive to events on input signals • specified in wait statements • resumes and schedules new values on output signals • schedules transactions • event on a signal if new value different from old value lect03.ppt ECE U530 F’06 13 lect03.ppt 14 ECE U530 F’06
ECEU530 Test Benches • Testing a design by simulation • Use a test bench model • an architecture body that includes an instance of the design under test • applies sequences of test values to inputs • monitors values on output signals • either using simulator • or with a process that verifies correct operation lect03.ppt ECE U530 F’06 15 Test Bench Example entity test_bench is end entity test_bench; architecture test_reg4 of test_bench is signal d0, d1, d2, d3, en, clk, q0, q1, q2, q3 : bit; begin dut : entity work.reg4(behav) port map ( d0, d1, d2, d3, en, clk, q0, q1, q2, q3 ); stimulus : process is begin d0 <= ’1’; d1 <= ’1’; d2 <= ’1’; d3 <= ’1’; wait for 20 ns; en <= ’0’; clk <= ’0’; wait for 20 ns; en <= ’1’; wait for 20 ns; clk <= ’1’; wait for 20 ns; d0 <= ’0’; d1 <= ’0’; d2 <= ’0’; d3 <= ’0’; wait for 20 ns; en <= ’0’; wait for 20 ns; … wait ; end process stimulus; end architecture test_reg4; lect03.ppt 16 ECE U530 F’06
ECEU530 Regression Testing • Test that a refinement of a design is correct • that lower-level structural model does the same as a behavioral model • Test bench includes two instances of design under test • behavioral and lower-level structural • stimulates both with same inputs • compares outputs for equality • Need to take account of timing differences lect03.ppt ECE U530 F’06 17 Regression Test Example architecture regression of test_bench is signal d0, d1, d2, d3, en, clk : bit; signal q0a, q1a, q2a, q3a, q0b, q1b, q2b, q3b : bit; begin dut_a : entity work.reg4(struct) port map ( d0, d1, d2, d3, en, clk, q0a, q1a, q2a, q3a ); dut_b : entity work.reg4(behav) port map ( d0, d1, d2, d3, en, clk, q0b, q1b, q2b, q3b ); stimulus : process is begin d0 <= ’1’; d1 <= ’1’; d2 <= ’1’; d3 <= ’1’; wait for 20 ns; en <= ’0’; clk <= ’0’; wait for 20 ns; en <= ’1’; wait for 20 ns; clk <= ’1’; wait for 20 ns; … wait ; end process stimulus; ... lect03.ppt 18 ECE U530 F’06
ECEU530 Regression Test Example … verify : process is begin wait for 10 ns; assert q0a = q0b and q1a = q1b and q2a = q2b and q3a = q3b report ”implementations have different outputs” severity error; wait on d0, d1, d2, d3, en, clk; end process verify; end architecture regression; lect03.ppt ECE U530 F’06 19 lect03.ppt 20 ECE U530 F’06
ECEU530 Synthesis • Register Transfer Level Synthesis: • Translates register-transfer-level (RTL) design into gate-level netlist • Restrictions on coding style for RTL model • Tool dependent • High Level Synthesis • Translate behavioral code to RTL level • Beyond the scope of this course • Logic Level Synthesis • Tranlate gate-level net list into implementation technology lect03.ppt ECE U530 F’06 21 Basic Design Methodology Requirements RTL Model Simulate Synthesize Gate-level Simulate Test Bench Model ASIC or FPGA Place & Route Timing Simulate Model lect03.ppt 22 ECE U530 F’06
ECEU530 Modeling Digital Systems: Definitions • System is made up of components connected by signals • Model interface to components (entity) and their behavior (architecture) • A signal carries logical values • logical values: ‘1’ and ‘0’ • these are abstractions for real voltage values • convenient for modeling digital systems • Signals change value over time • a change in value is an event • A time ordered sequence of events on a signal produces a waveform lect03.ppt ECE U530 F’06 23 Example: Half Adder Inputs Outputs a b s c . c = a b 0 0 0 0 s = a b + 0 1 1 0 1 0 1 0 1 1 0 1 c a s b Half adder lect03.ppt 24 ECE U530 F’06
ECEU530 Half Adder Timing a c a b s s b c time • Event on b: XOR evaluates causes s to change value • There is a propagation delay associated with a logic gate evaluating lect03.ppt ECE U530 F’06 25 Events and Signals • Event: 0 1 transition 1 0 transition • Signal values: 0, 1 • When simulator starts, signals are undefined: U • What happens if I have a short circuit? • Driving both 0 and 1 on same wire: X • (meaning for simulation, not for synthesis) • High Impedance output: Z • Don’t Care: � lect03.ppt 26 ECE U530 F’06
ECEU530 Signal Types • In VHDL all signals have types • We use the type std_logic • It is defined in a package: • ieee.std_logic_1164.all • It defines a std_logic signal to be able to have values: • 0, 1, X, U, Z, � and 3 others lect03.ppt ECE U530 F’06 27 Half Adder in VHDL • Describe entity, architecture library ieee; use ieee.std_logic_1164.all; entity half_adder is port (a,b: in std_logic; sum, carry: out std_logic); end entity half_adder; • half_adder is the name of the entity • port ( ); is the port list lect03.ppt 28 ECE U530 F’06
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