ECEU530 Homework 4 due Wednesday Oct 25 ECE U530 Digital Hardware - - PDF document

▶
eceu530
SMART_READER_LITE
LIVE PREVIEW

ECEU530 Homework 4 due Wednesday Oct 25 ECE U530 Digital Hardware - - PDF document

Mar 23, 2023 361 likes •520 views

ECEU530 Homework 4 due Wednesday Oct 25 ECE U530 Digital Hardware Synthesis Write a testbench for the ALU from Homework 3 Prof. Miriam Leeser mel@coe.neu.edu Write the MUX function from lecture 10 October 18, 2005 Write code that

slide-1
SLIDE 1

ECEU530

ECE U530 Digital Hardware Synthesis

  • Lecture 11:
  • Sequential Logic in VHDL
  • Finite State Machines in VHDL
  • Project proposals due now
  • HW 4 due Wednesday, October 25
  • Use the discussion board to post questions

ECE U530 F06

lect11.ppt

  • Prof. Miriam Leeser

mel@coe.neu.edu October 18, 2005

ECE U530 F’06 2

lect11.ppt

Homework 4 due Wednesday Oct 25

  • Write a testbench for the ALU from Homework 3
  • Write the MUX function from lecture 10
  • Write code that calls the MUX function

ECE U530 F’06 3

lect11.ppt

Schedule

  • Homework 4 due Wednesday, October 25
  • Review in class on Monday, October 30
  • Midterm in class on Wednesday, November 1
  • Homework 5: based on ECEU323 Lab 4

Due Wednesday November 8

ECE U530 F’06 4

lect11.ppt

VHDL for Synthesis with Xilinx

  • Documentation available from Xilinx:
  • link on course web page (External Links)
  • http://www.xilinx.com/support/sw_manuals/xilinx6/index.htm
  • From the PDF collection, we are interested in:

– Synthesis and Verification Design Guide – XST Users Guide

  • Some material in this lecture is from:
  • XST Users Guide Chapter 6 VHDL language support:

– Sequential Circuits

slide-2
SLIDE 2

ECEU530

ECE U530 F’06 5

lect11.ppt

Sequential HW in VHDL

  • We will describe synchronous, sequential hardware in

VHDL

  • Synchronous, sequential hardware is clocked
  • flip-flops
  • registers and shift registers
  • counters
  • state machines
  • I can describe sequential hardware with
  • sequential VHDL statements
  • concurrent VHDL statements

–signal assignments

  • same as combinational hardware

ECE U530 F’06 6

lect11.ppt

Combinational Hardware in VHDL

  • Process has no wait statements or clock signals
  • All signals on RHS of assignments appear in process

sensitivity list

  • Example of a good combinational HW description:

process(A, B, C) variable D: Std_Logic; begin if A='1' then D := B; else D := B or C; end if; F <= D; end process; A B C F

ECE U530 F’06 7

lect11.ppt

Good Combinational Techniques

  • All signals that effect result go in process sensity list
  • Any signal assigned in one branch is assigned in all

branches:

  • of a case statement
  • of if-then-else clause
  • Use case statements (NOT nested if-then-else

statements) to avoid inferring priority encoder

  • Use don’t cares to assign to outputs
  • Never use don’t cares in a comparison statement

ECE U530 F’06 8

lect11.ppt

Sequential Logic when you don’t want it

  • You can write combinational VHDL that synthesizes

to sequential hardware that you did not intend

  • No clock signal, no wait signal
  • latches are synthesized
  • If you use the VHDL term unaffected

–Why?

  • If you use the VHDL term null

–Why?

  • If you do NOT put the same assignment on every

branch of your if--then--else or CASE statements

–Why?

slide-3
SLIDE 3

ECEU530

ECE U530 F’06 9

lect11.ppt

GOOD If statement example

signal A, B, C, P1, P2, Y, Z: std_logic; process ( A, B, C, P1, P2 ) begin Y <= ‘0’; Z <= ‘1’; if (P1 = ‘1’) then Y <= A; elsif (P2 = ‘0’) then Y <= B; else Z <= C; end if; end process;

ECE U530 F’06 10

lect11.ppt

Null and Unaffected

case opcode is when add => Acc1 <= Acc + operand; when subtract => Acc1 <= Acc - operand; when nop => null; end case;

with sel select Z <= A when ‘0’, Z <= B when ‘1’, Z <= unaffected when others;

ECE U530 F’06 11

lect11.ppt

Sequential Logic when you want it

  • Process statement with Clock on sensitivity list or

wait statement

  • Wait statement or sensitivity list, never both
  • Clocked, sequential hardware with sensitivity list
  • Do NOT put all signals on Right hand side on sensitivity list
  • Do put on sensitivity list clock plus any asynchronous inputs:

–Clock, or – Clock and reset, or –Clock and set, or –Clock and reset and set

wait statements

  • wait can be used to suspend a process for a specified

time period

  • Example: Using wait in a testbench:
  • Can also wait on a signal or on an event

wait until clk’event wait until clk’event and clk = ‘1’ wait until clk’event and clk =’0’

  • - *********************************
  • - process for simulating the clock

process begin clk <= not(clk); wait for 20 ns; end process;

  • - *********************************
slide-4
SLIDE 4

ECEU530

ECE U530 F’06 13

lect11.ppt

Process Simulation

  • Process can have wait statement or sensitivity list,

but not both

  • If process has sensitivity list, process is executed
  • nce at simulation start up, and after that when a

signal on the sensitivity list changes

  • If process has has a wait statement, process is

executed at simulation start up, until wait statement is executed, then it suspends

  • Process “wakes up” when wait condition is met

ECE U530 F’06 14

lect11.ppt

Sequential vs. Combinational HW

  • Combinational Circuits
  • Output depends on current values of inputs only
  • No feedback
  • No memory
  • Sequential Hardware
  • Feedback
  • Output depends on current inputs and current state
  • Circuit has memory elements
  • Sequential Hardware = Combinational Hardware plus memory

elements: latches, flipflops, memories ...

ECE U530 F’06 15

lect11.ppt

Sequential Hardware in VHDL

  • Synchronous Only
  • Clock
  • May or may not have a reset signal
  • Sequential Hardware is defined with a particular

“style”

  • VHDL synthesis tool looks for hardware described

using that style, and translates it to flip-flops and combinational logic

  • Clock signal is special. Usually called “CLK”

ECE U530 F’06 16

lect11.ppt

D Latch in VHDL

  • - D_LATCH.VHD

library IEEE; use IEEE.std_logic_1164.all; entity d_latch is port ( EN, DATA: in STD_LOGIC; Q: out STD_LOGIC); end d_latch; architecture BEHAV of d_latch is begin LATCH: process (EN, DATA) begin if (EN = '1') then Q <= DATA; end if; end process; end BEHAV;

slide-5
SLIDE 5

ECEU530

ECE U530 F’06 17

lect11.ppt

D-Flipflop

library IEEE; use IEEE.std_logic_1164.all; entity d_ff is port ( CLK, DATA: in STD_LOGIC; Q: out STD_LOGIC ); end d_ff; architecture BEHAV of d_ff is begin process (CLK) begin if (CLK'event and CLK='1') then Q <= DATA; end if; end process; end BEHAV;

ECE U530 F’06 18

lect11.ppt

D-Flipflop with wait statement

library IEEE; use IEEE.std_logic_1164.all; entity d_ff is port ( CLK, DATA: in STD_LOGIC; Q: out STD_LOGIC ); end d_ff; architecture with_wait of d_ff is begin process begin wait until rising_edge(CLK); Q <= DATA; end process; end BEHAV;

ECE U530 F’06 19

lect11.ppt

Edge Detection Functions

FUNCTION rising_edge (SIGNAL s : std_logic) RETURN BOOLEAN IS BEGIN RETURN (s’EVENT AND (s = ’1’)); END; FUNCTION falling_edge (SIGNAL s : std_logic) RETURN BOOLEAN IS BEGIN RETURN (s'EVENT AND s = ’0’)); END; IMPORTANT: Use these only with the clk signal

ECE U530 F’06 20

lect11.ppt

D-FF with Reset

process (CLK, RST) begin if RST = '1' then Q <= ‘0’; elsif CLK'EVENT and CLK = '1' then Q <= Data; end if; end process;

  • Asynchronous Set is similar
slide-6
SLIDE 6

ECEU530

ECE U530 F’06 21

lect11.ppt

D-FF with Clock Enable

  • Not supported:

wait until CLOCK'event and CLOCK = '0' and ENABLE = '1' ;

  • Supported:

wait until CLOCK'event and CLOCK = '0' ; if ENABLE = '1' then ... process(Clk) begin if Clk'event and Clk='1' then -- or rising_edge(Clk) if ENABLE = '1' then Q <= DATA; end if; end if; end process;

ECE U530 F’06 22

lect11.ppt

D-FF with Asynchronous Reset and Synchronous Enable

process(Rst, Clk) begin if Rst = '0' then Q <= '0'; elsif rising_edge(Clk) then if EN = ’1’ then Q <= D; end if; end if; end process;

ECE U530 F’06 23

lect11.ppt

process(Clk) begin if rising_edge(Clk) then Q <= D; end if; end process;

  • - or --

process begin wait until rising_edge(CLK); Q <= D; end process

Clk Q D C D Q

Clocked Flip-flop

ECE U530 F’06 24

lect11.ppt

process(Rst, Clk) begin if Rst = '0' then Q <= '0'; elsif rising_edge(Clk) then Q <= D; end if; end process;

Q D C Clk D Q R Rst Active low

Active Low Reset on a FF

slide-7
SLIDE 7

ECEU530

ECE U530 F’06 25

lect11.ppt

Register (Eight-bit)

process(Clk) begin if rising_edge(Clk) then Q <= D; end if; end process; D (7 downto 0) Q(7 downto 0) Clk Clk Q(7) Q(6) Q(5) Q(1) Q(2) Q(3) Q(0) D(7) D(6) D(5) D(4) D(1) D(2) D(3) D(0) Q(4) This register has no reset

ECE U530 F’06 26

lect11.ppt

8 bit register

entity EXAMPLE is port (DI : in STD_LOGIC_VECTOR (7 downto 0); CLK : in STD_LOGIC; DO : out STD_LOGIC_VECTOR (7 downto 0)); end EXAMPLE; architecture ARCH1 of EXAMPLE is begin process (CLK) begin if CLK'EVENT and CLK = '1' then DO <= DI ; end if; end process; end ARCH1; architecture ARCH2 of EXAMPLE is begin process begin wait until CLK'EVENT and CLK = '1'; DO <= DI; end process; end ARCH2;

ECE U530 F’06 27

lect11.ppt

8 bit register with reset

entity EXAMPLE is port ( DI : in STD_LOGIC_VECTOR (7 downto 0); CLK : in STD_LOGIC; RST : in STD_LOGIC; DO : out STD_LOGIC_VECTOR (7 downto 0) ); end EXAMPLE; architecture ARCHI of EXAMPLE is begin process (CLK, RST) begin if RST = '1' then DO <= "00000000"; elsif CLK'EVENT and CLK = '1' then DO <= DI ; end if; end process; end ARCHI;

ECE U530 F’06 28

lect11.ppt

process(Clk) begin if rising_edge(Clk) then Q <= Q(6 downto 0) & Ser_In; end if; end process;

Shift Register (Eight-bit)

Ser_In Q(7 downto 0) Clk

slide-8
SLIDE 8

ECEU530

ECE U530 F’06 29

lect11.ppt

Ser_Out <= Q(7); process(Clk) begin if rising_edge(Clk) then if Load = '0' then Q <= D; else Q <= Q(6 downto 0) & '0'; end if; end if; end process;

Parallel-In/Serial-Out Shift Register (Eight-bit)

Ser_Out D Clk Load

signal D:Std_Logic_Vector(7 downto 0);

ECE U530 F’06 30

lect11.ppt

Count Q(7 downto 0) Clk process(Clk) begin if rising_edge(Clk) then if Count = '1' then Q <= Q + 1; end if; end if; end process;

Binary Counter (Eight-bit)

Note: The VHDL shown must have a function "+" defined to be complete. Count Q(7 downto 0) Clk "00000001" +

ECE U530 F’06 31

lect11.ppt

Counter with Asynchronous Reset

entity EXAMPLE is port (CLK : in STD_LOGIC; RST : in STD_LOGIC; DO : out STD_LOGIC_VECTOR (7 downto 0) ); end EXAMPLE; architecture ARCHI of EXAMPLE is begin process (CLK, RST) variable COUNT : STD_LOGIC_VECTOR (7 downto 0); begin if RST = '1' then COUNT := "00000000"; elsif CLK'EVENT and CLK = '1' then COUNT := COUNT + "00000001"; end if; DO <= COUNT; end process; end ARCHI;

ECE U530 F’06 32

lect11.ppt

What hardware gets inferred?

C <= A and B; D <= not C; process(Clk) begin if rising_edge(Clk) then Q_r <= D; end if; end process; A B C D Q D C Q_r Clk

slide-9
SLIDE 9

ECEU530

ECE U530 F’06 33

lect11.ppt

What hardware gets inferred?

process(Clk) begin if rising_edge(Clk) then C <= A and B; D <= not C; Q_r <= D; end if; end process;

A B

C D Q D clk Q_r Clk Q D clk Q D clk

ECE U530 F’06 34

lect11.ppt

C <= A and B after 5 ns; D <= not C after 10 ns; process(Clk) begin if rising_edge(Clk) then Q_r <= D; end if; end process;

CSAs with Processes (one flip-flop)

A B D C 0 ns 10 ns 40 ns 50 ns 60 ns 20 ns 30 ns Clk Q

A B C D Q D C Q_r Clk

ECE U530 F’06 35

lect11.ppt

C <= A_r and B_r after 5 ns; D <= not C after 10 ns; process(Clk) begin if rising_edge(Clk) then Q_r <= D; A_r <= A; B_r <= B; end if; end process;

CSAs with Processes (multiple flip-flops)

A B C D Q D C Q_r Clk Q D C Q D C A_r B_r

A B D C 0 ns 10 ns 40 ns 50 ns 60 ns 20 ns 30 ns Clk Q A_r B_r

ECE U530 F’06 36

lect11.ppt

slide-10
SLIDE 10

ECEU530

ECE U530 F’06 37

lect11.ppt

ECE U530 F’06 38

lect11.ppt

ECE U530 F’06 39

lect11.ppt

ECE U530 F’06 40

lect11.ppt

Sequential Hardware

  • Latches
  • Flip-Flops
  • Registers
  • Shift registers
  • Counters
  • Finite state machines
slide-11
SLIDE 11

ECEU530

ECE U530 F’06 41

lect11.ppt

Comb Ckt Next State Variables Present State Variables Input Memory Feedback

Sequential Hardware Model

Outputs

ECE U530 F’06 42

lect11.ppt

Finite State Machine State register Next state logic Output Logic This is a Moore machine Outputs depend on current state only Inputs Outputs

ECE U530 F’06 43

lect11.ppt

Finite State Machine

State register Next state logic Output Logic Inputs Outputs Moore machine: outputs depend on current state only Mealy machine: outputs depend on current state and inputs

ECE U530 F’06 44

lect11.ppt

State Machine Diagram State0 Out1<=‘0’ Out2<=‘1’ In1=‘0’ and In2=‘1’ Reset State Name Moore Machine Outputs Asynch reset will be shown

  • nce

Condition to transition between states

slide-12
SLIDE 12

ECEU530

ECE U530 F’06 45

lect11.ppt

STOPWATCH

RESET START_STOP CLEAR

Counter and Display

CE

Example: Stop Watch

Inputs: Start_stop, Reset Outputs: Count enable: advance time Clear: reset time

ECE U530 F’06 46

lect11.ppt

1 State Diagram

ECE U530 F’06 47

lect11.ppt

To Describe an FSM in VHDL

  • Next state function
  • Output function
  • State register to store current state
  • Each can be its own process
  • Which processes are combinational?
  • Which processes are sequential?

ECE U530 F’06 48

lect11.ppt

FSM Description in VHDL

architecture FSM of DEMO is type STATE_TYPE is ( … ); signal CURRENT_STATE, NEXT_STATE : STATE_TYPE; begin STATE_REG: process(CLK, RESET) ... end process; NEXT_STATE_LOGIC: process(CURRENT_STATE, <inputs>) ... end process; OUTPUT_LOGIC: process(CURRENT_STATE) ... end process; end FSM;

slide-13
SLIDE 13

ECEU530

ECE U530 F’06 49

lect11.ppt

library IEEE; use IEEE.std_logic_1164.all; entity STOPWATCH is port( CLK, RESET, START_STOP: in std_logic; CE, CLEAR: out std_logic); end STOPWATCH;

Stopwatch FSM Entity

STOPWATCH

RESET START_STOP CLEAR

Counter and Display

CE

ECE U530 F’06 50

lect11.ppt

architecture FSM of STOPWATCH is type STATE_TYPE is (ZERO, START, COUNT, STOP, STOPPED); ... begin ... end FSM;

Defining States

ECE U530 F’06 51

lect11.ppt

State Register is only Sequential Part

architecture FSM of STOPWATCH_CTRL is type STATE_TYPE is (ZERO, START, COUNT, STOP, STOPPED); signal CURRENT_STATE, NEXT_STATE : STATE_TYPE; begin STATE_REG: process(CLK, RESET) begin if (RESET = '0') then CURRENT_STATE <= ZERO; elsif (rising_edge(CLK)) then CURRENT_STATE <= NEXT_STATE; end if; end process; ... end FSM;

ECE U530 F’06 52

lect11.ppt

Next State Logic

NS_LOGIC: process (CURRENT_STATE, START_STOP) begin case CURRENT_STATE is when ZERO => if(START_STOP = '1')then NEXT_STATE <= START; else NEXT_STATE <= ZERO; end if; when START => if(START_STOP = '1')then NEXT_STATE <= START; else NEXT_STATE <= COUNT; end if; when COUNT => if(START_STOP = '1')then NEXT_STATE <= STOP; else NEXT_STATE <= COUNT; end if;

slide-14
SLIDE 14

ECEU530

ECE U530 F’06 53

lect11.ppt

Next State Logic (cont’d)

when STOP => if(START_STOP = '1')then NEXT_STATE <= STOP; else NEXT_STATE <= STOPPED; end if; when STOPPED => if(START_STOP = '1')then NEXT_STATE <= START; else NEXT_STATE <= STOPPED; end if; when others => NEXT_STATE <= ZERO; end case; end process;

ECE U530 F’06 54

lect11.ppt

Output Logic

OUTPUT_LOGIC: process(CURRENT_STATE) begin case CURRENT_STATE is when ZERO => CE <= '0'; CLEAR <= '1'; when START => CE <= '1'; CLEAR <= '0'; when COUNT => CE <= '1'; CLEAR <= '0'; when STOP => CE <= '0'; CLEAR <= '0'; when STOPPED => CE <= '0'; CLEAR <= '0'; when others => CE <= '0'; CLEAR <= '1'; end case; end process;

ECE U530 F’06 55

lect11.ppt

To Describe FSM in VHDL

  • Create an enumerated type for states
  • Three processes for behavior of FSM
  • 1. clocked process for state register
  • 2. combinational process for next state logic

sensitivity list : inputs and current state

  • 3. combination process for outputs

Moore Machine: sensitivity list: current state Mealy Machine: sensitivity list: current state and inputs Where does reset go?

ECE U530 F’06 56

lect11.ppt