ECE U530 Digital Hardware Synthesis Prof. Miriam Leeser - PDF document

ECEU530 ECE U530 Digital Hardware Synthesis Prof. Miriam Leeser mel@coe.neu.edu Sept 11, 2006 • Lecture 2: • CAD TOOLS: Xilinx and Modelsim • Levels of Design • VHDL Introduction lect02.ppt ECE U530 F06 Programming Assignments • All assignments are expected to represent individual work ! • Programming assignments will be done on the WinCOE system • Tools: • Xilinx ISE version 6.2i • Modelsim 5.7e • Programming Assignments will be submitted electronically on the COE system • You must have a COE account for this class lect02.ppt 2 ECE U530 F’06

ECEU530 WinCOE information • http://www.coe.neu.edu/computer/ has the information you need to get started • You must have a COE account for this class • Go to http://www.coe.neu.edu/computer/ then click on HELP! then click on Account Information For New Users • WinCOE computers are available on the second floor of Snell Engineering lect02.ppt ECE U530 F’06 3 Xilinx and Modelsim • I have the tools on a PC (at work or at home). Can I work there, then upload the solutions ? • Yes, but ... It is your responsibility to make sure: Your programs run under the WinCOE versions. i.e. no problems with incompatibilities, file formats, etc. • We will grade programs on the WinCOE system. It is your responsibility to make sure that they run there. • Version 6.2i of the Xilinx ISE tools • Version 5.7e of Modelsim lect02.ppt 4 ECE U530 F’06

ECEU530 Your files on WinCOE • The WinCOE system loads your COE home directory every time you log in • Create a directory for this course in your COE home directory: • Open an Explorer window (right click on Start and choose Explore) • Navigate to Coewin � � winusers � � User_Name � � � � This is your directory on the COE system • Create a new folder called 530local : right click in the directory and choose New � � Folder � � • (You may already have a folder called ECEU530) • Note: It is important that you not put empty spaces in any directory in the path for this course. The software tools do not recognize empty spaces. All names must be 8 characters or less. lect02.ppt ECE U530 F’06 5 Xilinx and Modelsim Tutorial • You should work through the ISE Quick Start Tutorial by Wednesday, September 23. • Start up the Xilinx tools, then click on: Help -> Tutorials -> ISE Quickstart and follow the instructions. I have also put a copy on Blackboard under Homework lect02.ppt 6 ECE U530 F’06

ECEU530 Projects • Describe a large system in VHDL, simulate with Modelsim • Work is expected to be individual • Deadlines • Oct 4: Tell me your project idea • Oct 18: Formal project proposal • Nov 8: Progress report • Nov 20: Preliminary project report • Dec 13: Final project report • Project ideas: • simple processor • robot controller • elevator controller lect02.ppt ECE U530 F’06 7 How to Describe Hardware Designs • Use CAD Tools • CAD Tools translate your design into a hardware architecture • Two types of design entry: • Schematic capture –This is what you used in ECE U322/ECEU323 • Hardware Description Language –This is what this class is about • CAD tools translate both types of descriptions to hardware lect02.ppt 8 ECE U530 F’06

ECEU530 The Need for HDLs • Technology trends • 1 billion transistor chip running at 3 GHz • Need for Hardware Description Languages • Systems become more complex • Design at the gate and flip-flop level becomes very tedious and time consuming • HDLs allow • Design and debugging at a higher level before conversion to the gate and flip-flop level • Tools for synthesis do the conversion • VHDL, Verilog are the most popular • VHDL – VHSIC Hardware Description Language lect02.ppt ECE U530 F’06 9 HDLs vs. Programming Languages • Procedural programming languages provide algorithms, or the how of implenting a design • for computation • for data manipulation • typically independent of the hardware it is running on • Hardware description languages describe a system • Interfaces are important • May want to describe in different ways –behavior –structure • May want to specify specific physical properties lect02.ppt 10 ECE U530 F’06

ECEU530 HDLs vs. Programming Languages (2) • Procedural programming languages: • sequential execution • structural information less important • exact timing information is NOT important • Hardware description languages: • Parallel execution • I/O ports, building blocks • Exact timing information IS important lect02.ppt ECE U530 F’06 11 Sequential vs. concurrent • This is a legal fragment of VHDL code • What order do these statements execute in? A <= B + C; C <= D + E; lect02.ppt 12 ECE U530 F’06

ECEU530 Why Describe a System? • Design Specification • Unambiguous definition of components and interfaces • Documentation • Design Simulation • verify performance prior to/after design implementation –functional correctness –timing • Design Synthesis • Automatic generation of a hardware design • Component and Design Reuse • Technology Independence lect02.ppt ECE U530 F’06 13 lect02.ppt 14 ECE U530 F’06

ECEU530 Domains and Levels of Modeling Structural Functional high level of abstraction low level of abstraction Geometric “Y-chart” due to Gajski & Kahn lect02.ppt ECE U530 F’06 15 Domains and Levels of Modeling Functional Structural Algorithm (behavioral) Register-Transfer Language Boolean Equation Differential Equation Geometric “Y-chart” due to Gajski & Kahn lect02.ppt 16 ECE U530 F’06

ECEU530 Domains and Levels of Modeling Structural Functional Processor-Memory Switch Register-Transfer Gate Transistor Geometric “Y-chart” due to Gajski & Kahn lect02.ppt ECE U530 F’06 17 Domains and Levels of Modeling Functional Structural Polygons Sticks Standard Cells Floor Plan Geometric “Y-chart” due to Gajski & Kahn lect02.ppt 18 ECE U530 F’06

ECEU530 Design Levels Level Type of Description Behavioral or Architectural Function of the system specified Level as pure behavior: a + b Register Transfer Level Registers, wires, adders, muxes, etc. required to implement behavior Logic or Gate Level Boolean logic equations and flip-flops Lower Levels: transistors, look How Boolean logic and flipflops up tables, ... are implemented lect02.ppt ECE U530 F’06 19 Abstraction levels and synthesis Architectural level Logic level Circuit level Layout level Behavioral level 0 State For I=0 to I=15 Sum = Sum + array[I] 0 0 0 Architecture Logic Circuit Layout synthesis synthesis synthesis synthesis Structural level Control Memory + (Library) Clk (register level) Ideal synthesis system lect02.ppt 20 ECE U530 F’06

ECEU530 lect02.ppt ECE U530 F’06 21 Language Syntax and Semantics • The syntax of a language is the set of strings that form legal programming constructs • External look of a language • Specified by a grammar • The semantics of a language describes the meaning of a language • Ideally the semantics is defined in terms of some abstract concept or mathematical model • various different ways to specify language semantics lect02.ppt 22 ECE U530 F’06

ECEU530 VHDL Syntax and Semantics • The VHDL standard specifies the syntax of VHDL, NOT the semantics • The semantics of VHDL is defined in terms of the VHDL simulator • Many constructs have no meaning without reference to how the VHDL simulator works: C <= A and B after 5 ns; lect02.ppt ECE U530 F’06 23 Introduction to VHDL • Developed originally by DARPA • for specifying digital systems • International IEEE standard (IEEE 1076-200x) • Last major revision is IEEE 1076-2001 • This is the version used in the class text • Hardware Description, Simulation, Synthesis • Provides a mechanism for digital design and reusable design documentation • Support different description levels • Structural (specifying interconnections of the gates), • Dataflow (specifying logic equations), and • Behavioral (specifying behavior) lect02.ppt 24 ECE U530 F’06

ECEU530 Introduction to VHDL (2) • Q: What does VHDL stand for? • A: VHSIC Hardware Description Language • Q: What is VHSIC? • A: Very High Speed Integrated Circuits • Q: What is VHDL used for? • A: To describe and test a digital circuit in a high level language environment. • VHDL is defined by IEEE Standard 1076 • The latest major language revision was in 2001 • VHDL enables hardware modeling from the gate to the system level • VHDL provides a mechanism for digital design and reusable design documentation lect02.ppt ECE U530 F’06 25 History of VHDL • Developed by IBM, Texas Instruments and Intermetrics as part of the DARPA funded VHSIC program in the 1980s • Standardized by the IEEE in 1987: • IEEE 1076-1987 • Last major language modification defined in 2001: • IEEE 1076-2001 • (IEEE 1076-1993 was previous major modification) • Standardized packages provide definitions of data types and expressions of timing data: • IEEE 1164 data types • IEEE 1076.3 numeric • IEEE 1076.4 timing lect02.ppt 26 ECE U530 F’06