ECEU530 Schedule ECE U530 Midterm in class on Wednesday, November - - PDF document

▶
eceu530
SMART_READER_LITE
LIVE PREVIEW

ECEU530 Schedule ECE U530 Midterm in class on Wednesday, November - - PDF document

Oct 30, 2023 225 likes •308 views

ECEU530 Schedule ECE U530 Midterm in class on Wednesday, November 1 Digital Hardware Synthesis Open book and notes Computers okay, but no running of CAD tools Prof. Miriam Leeser Classes on November 6 and 8 will be in 429 Dana

slide-1
SLIDE 1

ECEU530

ECE U530 Digital Hardware Synthesis

  • Lecture 14:
  • Review
  • Review Problems: FSMs in VHDL
  • Midterm in class Tuesday, November 1
  • HW 5: Due Wednesday, November 8
  • HW 6: Due Wednesday, November 15

ECE U530 F06

lect14.ppt

  • Prof. Miriam Leeser

mel@coe.neu.edu October 30, 2006

ECE U530 F’06 2

lect14.ppt

Schedule

  • Midterm in class on Wednesday, November 1
  • Open book and notes
  • Computers okay, but no running of CAD tools
  • Classes on November 6 and 8 will be in 429 Dana
  • Homework 5 due Wednesday, November 8
  • Write the Datapath for the calculator from ECEU323 in VHDL
  • Use the posted entity
  • Project progress report due Friday, November 10:
  • and email to me telling me where your project stands
  • some working VHDL code in your course account
  • Homework 6: Lab 5 due Wednesday November 15

ECE U530 F’06 3

lect14.ppt

What’s on the midterm

  • This material is in Handout 5: Midterm Information
  • The VHDL simulation model
  • VHDL types including bit, bit_vector, std_logic and

std_logic_vector

  • Modeling combinational circuits in VHDL using behavioral,

dataflow, and structural modeling

  • How to include a component from the Xilinx component library
  • Modeling sequential circuits in VHDL, including circuits with

clocks, synchronous resets, and asynchronous resets

  • flip-flops, registers, shift registers, counters
  • Modeling Mealy and Moore Machines in VHDL
  • Simulatable vs. synthesizable VHDL. Constructs that are

synthesizable by the design tools used in this class

  • Writing a testbench in VHDL

ECE U530 F’06 4

lect14.ppt

Midterm Reading

  • XST User Guide:
  • Chapter 2: HDL Coding Techniques

–We have not covered RAMds/ROMs and Black Boxes

  • Chapter 6: VHDL Language Support
  • Ashenden:
  • Chapters 1, 2 and 3
  • Chapter 4 Sections 4.1, 4.2, 4.3
  • Chapter 5
  • Chapter 7 Sections 7.4 and 7.5
  • Chapter 8 Sections 8.1, 8.2, 8.3
  • Chapter 11 Sections 11.1, 11.2
  • Chapter 13 Section 13.1
slide-2
SLIDE 2

ECEU530

ECE U530 F’06 5

lect14.ppt

Q1: 4 errors

library ieee; use ieee.std_logic_1164.all; entity my_ckt is port(CLK, RESET, EN, I1 : in std_logic; Q : out std_logic_vector(3 downto 0) ); end my_ckt; architecture behavioral of my_ckt is signal internal : std_logic_vector(1 to 4); begin if RESET then internal <= "1111"; elsif (CLK'event and (CLK = '1') and EN = '1') then internal <= I1 & internal(2 downto 0); end if; Q <= internal; end behavioral;

ECE U530 F’06 6

lect14.ppt

Q2a: VHDL Code

library IEEE; use IEEE.std_logic_1164.all; entity exam21 is port (D: in STD_LOGIC; EN: in STD_LOGIC; Q: out STD_LOGIC ); end exam21; architecture exam21_arch of exam21 is begin process(D, EN) begin if EN = '1' then Q <= D; end if; end process; end exam21_arch;

ECE U530 F’06 7

lect14.ppt

Q2a: Timing Diagram

EN D Q

ECE U530 F’06 8

lect14.ppt

Q2b: VHDL Code

entity exam22 is port (D: in STD_LOGIC; CLK: in STD_LOGIC; Reset: in STD_LOGIC; Q: out STD_LOGIC ); end exam22; architecture exam22_arch of exam22 is begin process(D, CLK, Reset) begin if Reset = '1' then Q <= ‘0’; elsif CLK’EVENT and CLK = ‘1’ then Q <= D; end if; end process; end exam22_arch;

slide-3
SLIDE 3

ECEU530

ECE U530 F’06 9

lect14.ppt

Q2b: Timing Diagram

Reset CLK D Q

ECE U530 F’06 10

lect14.ppt

Q2c

  • Part (a) has no reset signal. Is one needed? Why or why

not?

ECE U530 F’06 11

lect14.ppt

Q3: VHDL code

entity mygate is port (A, B, C, D : in STD_LOGIC; Y: out STD_LOGIC); end mygate; architecture structural of mygate is component nand2 port (i0,i1: in std_logic;

  • : out std_logic);

end component; signal y1,y2: STD_LOGIC; begin u1: nand2 port map (i0 => A, i1 => B, o => y1); u2: nand2 port map (i0 => C, i1 => D, o => y2); u3: nand2 port map (i0 => y1, i1 => y2, o => Y); end structural;

ECE U530 F’06 12

lect14.ppt

Q3:a

  • Draw the schematic that is defined by the VHDL code.
slide-4
SLIDE 4

ECEU530

ECE U530 F’06 13

lect14.ppt

Q3:b

  • Write a Boolean logic function for the function Y. Simplify

it as much as possible.

ECE U530 F’06 14

lect14.ppt

Q3:c

  • When you simulate the circuit, the signal y1 does not

appear in your simulation. Why not?

  • Explain why the input ports for the logic gate are named i0

and i1. Can they be named something else?

ECE U530 F’06 15

lect14.ppt

Q4: VHDL Code: entity

library IEEE; use IEEE.std_logic_1164.all; entity seq_circuit is port ( X: in STD_LOGIC; Y: in STD_LOGIC; CLK: in STD_LOGIC; RESET: in STD_LOGIC; Z: out STD_LOGIC ); end seq_circuit;

ECE U530 F’06 16

lect14.ppt

Q4: VHDL Code (1 of 3 )

architecture seq_circuit_arch of seq_circuit is type state_type is (A, B); signal state, next_state:state_type; begin state_register:process (CLK, RESET) begin if RESET='1' then state <= A; elsif (CLK'event and CLK='1') then state <=next_state; end if; end process;

slide-5
SLIDE 5

ECEU530

ECE U530 F’06 17

lect14.ppt

Q4: VHDL Code (2 of 3)

process (X, Y, state) begin case state is when A => if (X='1' and Y='0') then next_state <= B; else next_state <= A; end if; when B => if (Y='1') then next_state <= A; else next_state <= B; end if; end case; end process;

ECE U530 F’06 18

lect14.ppt

Q4: VHDL Code (3 of 3)

end process; process (X, state) begin case state is when A => Z <= X; when B => Z <= not X; end case; end process; end seq_circuit_arch;

ECE U530 F’06 19

lect14.ppt

Q4: a

  • Draw the entity for this circuit.

ECE U530 F’06 20

lect14.ppt

Q4:b

  • Draw the state diagram for this circuit. Clearly label all

inputs, states and outputs. Show the behavior on reset.

slide-6
SLIDE 6

ECEU530

ECE U530 F’06 21

lect14.ppt

Q4:c

  • Is this a Mealy machine or a Moore Machine? Explain

your answer.

ECE U530 F’06 22

lect14.ppt

Q5

  • Write VHDL code to implement an S-R flipflop with

asynchronous reset. The table for an S-R flip flop is given below. A D in the table indicates a don’t care, and an X indicates an error state.

S R Q Q* 1 1 1 D 1 D 1 1 1 D X

ECE U530 F’06 23

lect14.ppt

Q5: entity

entity SRFF is port (S: in STD_LOGIC; R: in STD_logic; Reset: in STD_LOGIC; CLK: in STD_LOGIC; Q: out STD_LOGIC ); end SRFF;

ECE U530 F’06 24

lect14.ppt

To Describe an FSM in VHDL

  • Next state function
  • Output function
  • State register to store current state
  • Each can be its own process
  • State register is ONLY sequential process
  • Next state, output are purely combinational
  • Can combine these into one process
slide-7
SLIDE 7

ECEU530

ECE U530 F’06 25

lect14.ppt

J-K Flip-Flop

ECE U530 F’06 26

lect14.ppt

JK FlipFlop in VHDL

ECE U530 F’06 27

lect14.ppt

Odd Parity Generator

  • Input is a stream of bits
  • Output is 1 if odd number of ones seen on input
  • 0 otherwise

ECE U530 F’06 28

lect14.ppt

Odd Parity Generator in VHDL

slide-8
SLIDE 8

ECEU530

ECE U530 F’06 29

lect14.ppt

String Recognizer Example

  • Recognize the string: 1011
  • Input:

1 0 0 1 0 1 1 0 1 1 0 0 1 0

  • Output:
  • State Diagram:

ECE U530 F’06 30

lect14.ppt

String Recognizer in VHDL