Lecture 13: Sequential Networks Flip flops and Finite State - - PowerPoint PPT Presentation

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Lecture 13: Sequential Networks Flip flops and Finite State - - PowerPoint PPT Presentation

Sep 26, 2023 114 likes •420 views

Lecture 13: Sequential Networks Flip flops and Finite State Machines CSE 140: Components and Design Techniques for Digital Systems Diba Mirza Dept. of Computer Science and Engineering University of California, San Diego 1 T Flip-Flop

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Lecture 13: Sequential Networks – Flip flops and Finite State Machines

CSE 140: Components and Design Techniques for Digital Systems

Diba Mirza

  • Dept. of Computer Science and Engineering

University of California, San Diego

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T CLK Q Q’

Characteristic Expression Q(t+1) = Q’(t)T(t) + Q(t)T’(t)

0 0 1 1 1 0 PS T 0 1 State table Q(t+1)

T Flip-Flop (Toggle)

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Using a JK F-F to implement a D and T F-F

J K Q Q’ x CLK

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iClicker The above circuit behaves as which of the following flip flops?

  • A. D F-F
  • B. T F-F
  • C. None of the above
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Using a JK F-F to implement a T F-F

J K Q Q’ T CLK T flip flop

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Flip flops

  • Write the state-table of the following flip-flops

– D – JK – T

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Combinational

CLK CLK A B C D

Sequential Networks

  • 1. Components F-Fs
  • 2. Specification
  • 3. Implementation: Excitation Table

S(t) X Y CLK

RTL: Register-Transfer Level Description

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Specification

  • Combinational Logic

– Truth Table – Boolean Expression – Logic Diagram (No feedback loops)

  • Sequential Networks: State Diagram (Memory)

– State Table and Excitation Table – Characteristic Expression – Logic Diagram (FFs and feedback loops)

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What we will learn:

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  • 1. Describe the desired behavior of a sequential circuit over time

(FSMs)

  • 2. Given the behavior of a sequential circuit, implement the circuit

Wall-E is a Finite State Machine

Active Inactive

Describing Wall-E Implementing Wall-E

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Finite State Machines: Describing circuit behavior over time

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2 bit Counter Symbol/ Circuit

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Finite State Machines: Describing circuit behavior over time

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Free running 2 bit Counter Symbol/ Circuit Output over time time

CLK Q1 Q0

What is the expected output of the counter over time?

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Finite State Machines: Describing circuit behavior over time

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2 bit Counter 00 Symbol/ Circuit Diagram that depicts behavior over time 01 10 11

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State: What is it ? Why do we need it?

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Symbol/ Circuit Behavior over time time

CLK

2 bit Counter PI Q: At time t1, what information is needed to produce the output of the counter at the next rising edge of the clock (i.e t2)?

  • A. All the outputs of the counter until t1
  • B. The initial output of the counter at time t=0
  • C. The output of the counter at current time t1
  • D. We cannot determine the output of the counter at t2 prior to t2

t1 t2

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Implementing the 2 bit counter

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S0 S1 S2 S3

State Diagram State Table

Q1(t) Q0(t) Q1(t+1) Q0(t+1) Current state Next State S0 S1 S1 S2 S2 S3 S3 S0

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State Table

Q1(t) Q0(t) Q1(t+1) Q0(t+1) 1 1 1 1 1 1 1 1

PI Q: Which of the following is the likely structure of the circuit realization of the counter Q0(t) Q1(t)

D Q Q’ D Q Q’

CLK Circuit with 2 flip flops B.

Combinational circuit Combinational circuit

Circuit with no flip flops A.

Q0(t) Q1(t)

Q D Q Q’

CLK Circuit with one flip flop C.

Combinational circuit

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State Table

Q1(t) Q0(t) Q1(t+1) Q0(t+1) 1 1 1 1 1 1 1 1

Q0(t) Q1(t)

D Q Q’ D Q Q’

CLK Circuit with 2 flip flops B.

Combinational circuit D0(t) = Q0(t)’ D1(t) = Q0(t) Q1(t)’ + Q0(t)’ Q1(t)

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State Table

Q1(t) Q0(t) Q1(t+1) Q0(t+1) 1 1 1 1 1 1 1 1

We store the current state using D-flip flops so that:

  • Inputs to the combinational circuit

don’t change while the next output is being computed

  • The transition to the next state
  • nly occurs at the rising edge of

the clock Q0(t) Q1(t)

D Q Q’ D Q Q’

CLK Implementation of 2-bit counter

Q0(t+1) = Q0(t)’ Q1(t+1) = Q0(t) Q1(t)’ + Q0(t)’ Q1(t)

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Generalized Model of Sequential Circuits

S(t) X Y CLK

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Let’s implement our free running 2-bit counter using T-flip flops

id Q1(t) Q0(t) T1(t) T0(t) Q1(t+1) Q0(t+1) 1 1 1 1 2 1 1 1 3 1 1

Excitation table

Q0(t) Q1(t)

T Q Q’ T Q Q’

CLK Circuit with 2 T-flip flops

Combinational circuit

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Let’s implement our free running 2-bit counter using T-flip flops

id Q1(t) Q0(t) T1(t) T0(t) Q1(t+1) Q0(t+1) 1 1 1 1 1 1 1 2 1 1 1 1 3 1 1 1 1

Excitation table

Q0(t) Q1(t)

T Q Q’ T Q Q’

CLK Circuit with 2 T-flip flops

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Let’s implement our free running 2-bit counter using T-flip flops Excitation table

T0(t) = T1(t) =

id Q1(t) Q0(t) T1(t) T0(t) Q1(t+1) Q0(t+1) 1 1 1 1 1 1 1 2 1 1 1 1 3 1 1 1 1

Q0(t) Q1(t)

T Q Q’ T Q Q’

CLK Circuit with 2 T-flip flops

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T Q Q’ T Q Q’

Q0 Q1 1 T1

Free running counter with T flip flops

T0(t) = 1 T1(t) = Q0(t)

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Let’s implement our free running 2-bit counter using JK-flip flops

id Q1(t) Q0(t) J1(t) K1(t) J0(t) K0(t) Q1(t+1) Q0(t+1) 1 1 1 1 2 1 1 1 3 1 1

Excitation table

Q0(t) Q1(t)

Q Q’ Q Q’

CLK Circuit with 2 JK-flip flops

Combinational circuit

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Let’s implement our free running 2-bit counter using JK-flip flops

id Q1(t) Q0(t) J1(t) K1(t) J0(t) K0(t) Q1(t+1) Q0(t+1) X 1 1 1 1 X 1 2 1 X 1 1 3 1 1 X 1

Excitation table

Q0(t) Q1(t)

Q Q’ Q Q’

CLK Circuit with 2 JK-flip flops

Combinational circuit

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Let’s implement our free running 2-bit counter using JK-flip flops

id Q1(t) Q0(t) J1(t) K1(t) J0(t) K0(t) Q1(t+1) Q0(t+1) X 1 X 1 1 1 1 X X 1 1 2 1 X 1 X 1 1 3 1 1 X 1 X 1

Excitation table

Q0(t) Q1(t)

Q Q’ Q Q’

CLK Circuit with 2 JK-flip flops

Combinational circuit

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Let’s implement our free running 2-bit counter using JK-flip flops

id Q1(t) Q0(t) J1(t) K1(t) J0(t) K0(t) Q1(t+1) Q0(t+1) X 1 X 1 1 1 1 X X 1 1 2 1 X 1 X 1 1 3 1 1 X 1 X 1

Excitation table

Q0(t) Q1(t)

Q Q’ Q Q’

CLK Circuit with 2 JK-flip flops

Combinational circuit

J1(t) = Q0(t) K1(t) = Q0(t) J0(t) = 1 K0(t) =1