Lecture 12: Sequential Networks – Flip flops and registers
CSE 140: Components and Design Techniques for Digital Systems
Diba Mirza
- Dept. of Computer Science and Engineering
University of California, San Diego
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Lecture 12: Sequential Networks Flip flops and registers CSE - - PowerPoint PPT Presentation
Lecture 12: Sequential Networks Flip flops and registers CSE 140: Components and Design Techniques for Digital Systems Diba Mirza Dept. of Computer Science and Engineering University of California, San Diego 1 D Flip-Flop vs. D Latch
Diba Mirza
University of California, San Diego
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CLK D Q (latch) Q (flop) 2
Id D Q(t) Q(t+1) 0 0 0 0 1 0 1 0 2 1 0 1 3 1 1 1
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What does the equation mean?
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PS
JK 00 01 11 10
Q(t+1)
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Characteristic Expression Q(t+1) = Q(t)K’(t)+Q’(t)J(t)
Sounds a lot like a latch I know…
PS
JK 00 01 11 10
Q(t+1)
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Characteristic Expression Q(t+1) = Q(t)K’(t)+Q’(t)J(t)
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15 0 4 12 8 1 5 13 9 3 7 15 11 2 6 14 10
0 4 12 8 1 5 13 9 3 7 15 11 2 6 14 10
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