Lecture 12: Sequential Networks Flip flops and registers CSE - - PowerPoint PPT Presentation

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Lecture 12: Sequential Networks Flip flops and registers CSE - - PowerPoint PPT Presentation

Lecture 12: Sequential Networks Flip flops and registers CSE 140: Components and Design Techniques for Digital Systems Diba Mirza Dept. of Computer Science and Engineering University of California, San Diego 1 D Flip-Flop vs. D Latch


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Lecture 12: Sequential Networks – Flip flops and registers

CSE 140: Components and Design Techniques for Digital Systems

Diba Mirza

  • Dept. of Computer Science and Engineering

University of California, San Diego

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D Flip-Flop vs. D Latch

CLK D Q Q

D Q Q

CLK D Q (latch) Q (flop) 2

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D Flip-Flop (Delay)

D CLK Q Q’

Id D Q(t) Q(t+1) 0 0 0 0 1 0 1 0 2 1 0 1 3 1 1 1

Characteristic Expression Q(t+1) = D(t)

0 0 1 1 0 1 PS D 0 1 State table NS= Q(t+1)

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What does the equation mean?

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SLIDE 4

iClicker

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How long does a D-flip flop store a bit before its

  • utput can potentially change?
  • A. Half a clock cycle
  • B. One clock cycle
  • C. Two clock cycles
  • D. There is no minimum time
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JK F-F

J CLK Q Q’ 0 0 0 1 1 1 1 0 0 1

PS

JK 00 01 11 10

State table

Q(t+1)

K

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Characteristic Expression Q(t+1) = Q(t)K’(t)+Q’(t)J(t)

Sounds a lot like a latch I know…

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SLIDE 6

JK F-F

J CLK Q Q’ 0 0 0 1 1 1 1 0 0 1

PS

JK 00 01 11 10

State table

Q(t+1)

K

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Characteristic Expression Q(t+1) = Q(t)K’(t)+Q’(t)J(t)

J K

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SLIDE 7

T CLK Q Q’

Characteristic Expression Q(t+1) = Q’(t)T(t) + Q(t)T’(t)

0 0 1 1 1 0 PS T 0 1 State table Q(t+1)

T Flip-Flop (Toggle)

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Using a JK F-F to implement a D and T F-F

J K Q Q’ x CLK

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iClicker The above circuit behaves as which of the following flip flops?

  • A. D F-F
  • B. T F-F
  • C. None of the above
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SLIDE 9

Using a JK F-F to implement a D and T F-F

J K Q Q’ T CLK T flip flop

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SLIDE 13

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Midterm review

True or False

  • 1. In a K-map an implicant can consist of a group of two adjacent

cells containing zeros

  • 2. A minterm may evaluate to a one for multiple input combinations.
  • 3. An incompletely specified function results in a minimal circuit

whose output cannot be determined for some input combinations.

  • 4. When minimizing a function to product of sum form, we always

assume that the don't care terms are 1.

  • 5. The output of combinational circuits depends only on current

inputs.

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Reduce to SOP form

F(a,b,c,d)=ΠM(3,4,5,6,7,11,12). ΠD(10, 15)

15 0 4 12 8 1 5 13 9 3 7 15 11 2 6 14 10

ab cd 00 01 00 01 11 10 11 10

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SLIDE 16

Reduce the following to a SOP form

0 4 12 8 1 5 13 9 3 7 15 11 2 6 14 10

1 0 0 1 1 0 1 1 0 0 X 0 1 0 1 X

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ab cd 00 01 00 01 11 10 11 10

F(a,b,c,d)=ΠM(3,4,5,6,7,11,12). ΠD(10, 15)

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Minimize using Boolean algebra

  • F(x,y,z)= xy+y’((x+y’)’+z)+xz

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Design Problem

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Design a circuit that gives the absolute distance between two 2-bit numbers ( e.g. x=3, y=1, d=2)

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Design Problem

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