SLIDE 1
Latches, Flip-flops, Registers, Memory
Sequential logic: elements to store values Output depends on inputs and stored values. (vs. combinational logic: output depends only on inputs)
Latch: CC-BY Rberteig@flickr
Latches, Flip-flops, Registers, Memory Sequential logic: elements to - - PowerPoint PPT Presentation
Latches, Flip-flops, Registers, Memory Sequential logic: elements to - - PowerPoint PPT Presentation
Latch: CC-BY Rberteig@flickr Latches, Flip-flops, Registers, Memory Sequential logic: elements to store values Output depends on inputs and stored values . (vs. combinational logic: output depends only on inputs) Processor: Data Path Components
SLIDE 2
SLIDE 3
Bistable latches
Q Q
Suppose we somehow get a 1 (or a 0?) on here.
Q Q
=
SLIDE 4
SR latch
Q Q R S Set Reset S R Q Q' Q (stable) Q' (stable) 1 1 1 1 1 ? ? 1 1 ? ? 1
SLIDE 5
SR latch
Q Q R S Q Q R S Q Q R S R S Q Q R S Q Q
SLIDE 6
if C = 0, then SR latch stores current value of Q. if C = 1, then D flows to Q: if D = 0, then R = 1 and S = 0, Q = 0 if D = 1, then R = 0 and S = 1, Q = 1
D latch
D C R S Q Q Clock Data bit
SLIDE 7
Time matters!
D C Q
Assume Q has an initial state of 0
ex
SLIDE 8
Clocks
Clock: free-running signal with fixed cycle time = clock period = T. Clock frequency = 1 / clock period A clock controls when to update a sequential logic element's state.
Clock period Falling edge Rising edge
SLIDE 9
Synchronous systems
Inputs to state elements must be valid on active clock edge. State element 1 State element 2 Combinational logic
SLIDE 10
D flip-flop with falling-edge trigger
D C Q E
QL DL CL
D latch
QL QF DF CF
D latch
QF
Q
leader follower
Clock
leader stores D as E folower stores E as Q Can still read Qnow Qnext becomes Qnow
Time
SLIDE 11
Time matters!
D C E Q
Assume Q and E have an initial state of 0
ex
SLIDE 12
Reading and writing in the same cycle
Assume Q is initially 0.
Q D C D Flip-Flop Q Clock
SLIDE 13
D flip-flop = one bit of storage
Q D C D Flip-Flop Q 1
SLIDE 14
A 1-nybble* register
(a 4-bit hardware storage cell) Write Clock
1 1 Q D C D Flip-Flop Q Q D C D Flip-Flop Q Q D C D Flip-Flop Q Q D C D Flip-Flop Q
*Half a byte!
SLIDE 15
Register file
Read ports Why 2?
Read register selector 1 Read register selector 2 Write register selector Write data Write? Read data 1 Read data 2
r r r w w w
r = log2 number of registers w = bits in word
Array of registers, with register selectors, write/read control, input port for writing data, output ports for reading data. Write port
0 = read 1 = write
SLIDE 16
Read ports (data out)
Read register number 1 Register 0 Register 1 . . . Register n – 2 Register n – 1 M u x Read register number 2 M u x Read data 1 Read data 2
SLIDE 17
Write 1 n-to-2n decoder n – 2 n – 1 Register 0 C D Register 1 C D Register n – 2 C D Register n – 1 C D . . . Register number . . . Register data
Write port (data in)
incoming data register number write control clock
SLIDE 18
RAM (Random Access Memory)
Similar to register file, except… A B
SLIDE 19
16 x 4 RAM
4 to 16 decoder data
- ut
1101
20