ECEU530 Projects ECE U530 Individual project implementing a design - PDF document

ECEU530 Projects ECE U530 • Individual project implementing a design in VHDL Digital Hardware Synthesis • Team projects if the parts are well defined • Complexity about the same as the calculator in ECEU323 Prof. Miriam Leeser mel@coe.neu.edu • Some project ideas: October 11, 2006 • A simple computer • An elevator controller • Lecture Today is in 429 DANA! • A robot controller • Homework 3: ALU • VHDL arithmetic • Deadlines: • Types • October 9: Send me your idea • Reading: Sections 4.1, 4.2, 8.4, 8.5 • October 18: Write a short project proposal • Email me your project idea by Tuesday October 10! • Nov 8: Progress Report • Homework 3 due October 18 • Nov 20: Preliminary Project Report • Project Proposals due October 18 • Dec 13: Final Project Report Due lect09.ppt lect09.ppt ECE U530 F06 2 ECE U530 F’06 Project Proposal (Handout 4) Homework 3 due Wed, October 18 • Description of what you will describe in VHDL • Write a VHDL description of the ALU • A detailed plan of how you will implement your from ECEU323 lab 3 project • Your solution should include: • Several different implementations, each adding more functionality • An entity that describes the interface of the ALU • Example: Elevator controller • Some ports are std_logic and some ports are std_logic_vector –1 elevator, 2 floors, only up and down buttons at each floor • An architectural body for the ALU –add buttons inside the elevator • You may use any technique you wish –add open/close door functionality • What is hard? –add more floors, more elevators ... • Getting the arithmetic right • Specification of all inputs and outputs you anticipate • Carry, borrow and overflow • Writing the testbench • Entity in VHDL • Homework 4 will ask you to write a testbench for your ALU • Schedule for the rest of the semester lect09.ppt lect09.ppt 3 ECE U530 F’06 4 ECE U530 F’06

ECEU530 ALU ALU Operation • Interface: • Architecture: • Interface signals should be std_logic_vector or std_logic • Operation depends on inputs S2, S1, S0 • VHDL architecture body should be a case statement lect09.ppt lect09.ppt 5 ECE U530 F’06 6 ECE U530 F’06 VHDL Case Statement Numeric Packages • Your code should start with (default in Xilinx): case <expression> is when <choices> => <statements> library IEEE; when <choices> => <statements> use IEEE.std_logic_1164.all; when others => <statements> use ieee.std_logic_arith.all; end case; use ieee.std_logic_unsigned.all; • All possible values of expression must be covered • std_logic_1164 defines std_logic, std_logic_vector • Exactly one choice should be true • std_logic_unsigned defines unsigned arithmetic on standard logic vector • Statements can be one or more VHDL statements • std_logic_arith defines signed two’s complement • Good coding style for synthesis: data types and arithmetic and unsigned data types • Assign to the same signals in every branch of a case and arithmetic statement lect09.ppt lect09.ppt 7 ECE U530 F’06 8 ECE U530 F’06

ECEU530 ALU Arithmetic Arithmetic Operators • Convert std_logic_vectors to signed or unsigned first • Should you use unsigned, signed or std_logic_vector for your ALU? • The bits will be the same signal A: std_logic_vector(3 downto 0); • signed and unsigned are really ways to annotate your code signal A_unsigned: unsigned(3 downto 0); with the type of arithmetic you are doing A_unsigned <= unsigned(A); • For ALU, are you doing signed or unsigned arithmetic? A <= std_logic_vector(A_unsigned); –Hint: Look at Flag • Important: You do NOT need the single quote! • unsigned() and std_logic_vector() are type conversion functions • they are overloaded functions • std_logic_vector() is defined differently for parameters of type signed and unsigned lect09.ppt lect09.ppt 9 ECE U530 F’06 10 ECE U530 F’06 Carry out Carry Out and Overflow • Suppose want carry out from result? • If you add two unsigned numbers, you may get a carry out from the MSB • Need to make result one bit longer than inputs • Carry out means that you have overflowed the range of an • but type of RHS and LHS must match. unsigned value • Extend RHS signals by one bit using concatenation: • Two inputs, A, B are 4 bits, Result is too big for 4 bits • • If you add two signed numbers you may get an signal A8, B8, Result8 : unsigned(7 downto 0); overflow from the MSB signal Result9 : unsigned(8 downto 0); • Overflow means that you have overflowed the range of a -- Carry out in result signed value Result9 <= (‘0’ & A8) + (‘0’ & B8); • Overflow is different from Carry Out • You can have overflow and no carry out, carry out and no overflow lect09.ppt lect09.ppt 11 ECE U530 F’06 12 ECE U530 F’06

ECEU530 Carry out and overflow Carry out and overflow • 5, 7, -5, -7 represented as 4 bit, signed values: • 5, 7, -5, -7 represented as 4 bit, signed values: • 0101 0111, 1011, 1001 • 0101 0111, 1011, 1001 5 + 7 - 5 + 7 111 111 0101 1011 0111 0111 1100 overflow, no carry out 10010 no overflow, carry out 5 -7 -5 -7 1 11 0101 1011 1001 1001 1110 no overflow, no carry out 10100 overflow, carry out lect09.ppt lect09.ppt 13 ECE U530 F’06 14 ECE U530 F’06 Adder with Carry In Detecting overflow and carry out • Detecting carry out is easy want to calculate: ??? <= A(3:0) + B(3:0) + CarryIn • convert signals to unsigned • extend inputs by concatenating a zero to the MSB • if MSB of result is 1 then you have carry out signal A, B, Result : unsigned(3 downto 0); signal Y5 : unsigned(4 downto 0); signal CarryIn : std_logic; • How do you detect overflow? -- Carry out and Result in Y5 Y5 <= (A & ‘1’) + (B & CarryIn); • For ALU, only need overflow for negation Result <= Y5( 4 downto 1); • How do you calculate overflow? • How do you compute borrow on subtraction? This gives the correct result • borrow = not(carryout) lect09.ppt lect09.ppt 15 ECE U530 F’06 16 ECE U530 F’06

ECEU530 Testing your design Testbench Example: Adder • Test bench for adder that tests all possible Library IEEE; combinations use IEEE.STD_LOGIC_1164.all; use IEEE.STD_LOGIC_ARITH.all; use IEEE.std_logic_unsigned.all; • For ALU, do NOT want to test: Library WORK; use WORK.all; • all inputs x all outputs x all functions entity testbench is end testbench; • What should you test? architecture test of testbench is signal clk : std_logic:= '0'; signal rst : std_logic:= '0'; signal data_in1:std_logic_vector(4 downto 0); signal data_in2:std_logic_vector(4 downto 0); signal data_out:std_logic_vector(4 downto 0); lect09.ppt lect09.ppt 17 ECE U530 F’06 18 ECE U530 F’06 Testbench Example (2) Testbench Example (4) component adder process port( variable i : integer; in1 : in std_logic_vector(3 downto 0); variable j : integer; in2 : in std_logic_vector(3 downto 0); begin out : out std_logic_vector(4 downto 0)); for i in 0 to 15 loop end component; for j in 0 to 15 loop a <= CONV_STD_LOGIC_VECTOR(i, 4); signal a : std_logic_vector(3 downto 0); b <= CONV_STD_LOGIC_VECTOR(j, 4); signal b : std_logic_vector(3 downto 0); wait for 20 ns; signal c : std_logic_vector(4 downto 0); end loop; end loop; begin end process; --****************************************** add1 : adder end test; port map( in1 => a, CONV_STD_LOGIC_VECTOR is defined in package ieee.std_logic_arith in2 => b, out => c ); lect09.ppt lect09.ppt 19 ECE U530 F’06 20 ECE U530 F’06

ECEU530 Input Stimuli Exercise • What should inputs be? • Write an adder and test it using the testbench • All possible combinations • Use VHDL loops to generate these • May be too long or complex for some applications • Test important cases to verify design functionality –Example: ALU »Test each type of operation with different inputs » Test boundary cases »Make sure each input and output bit is tested »overflow, ... • Can use same testbench for specified and synthesized design lect09.ppt lect09.ppt 21 ECE U530 F’06 22 ECE U530 F’06 User defined integer types - Examples User-defined enumeration types - Examples type day_of_month is range 0 to 31 ; type state is (S0, S1); type year is range 0 to 2100; type alu_function is (nop, add, subtract,multiply, divide); type set_index_range is range 999 downto 100; type octal_digit is (‘0’, ‘1’, ‘2’, ‘3’, ‘4’, ‘5’, ‘6’, ‘7’); constant number_of_bits: integer :=32; type bit_index is range 0 to number_of_bits-1; type mixed is (lf, cr, ht, ‘-’, ‘/‘, ‘\’); Values of bounds can be expressions, but Each value in an enumeration type must be either need to be known when the model is analyzed. an identifier or a character literal lect09.ppt lect09.ppt 23 ECE U530 F’06 24 ECE U530 F’06