Spiral 2-5 Sequential Logic Constructs 2-5.2 Learning Outcomes I - PowerPoint PPT Presentation

2-5.1 Spiral 2-5 Sequential Logic Constructs

2-5.2 Learning Outcomes • I understand how a bistable works – I understand how a bistable holds, sets, and resets • I understand the issues that glitches pose to bistables and the need for latches • I understand the difference between level- sensitive and edge-sensitive • I understand how to create an edge-triggered FF from 2 latches

2-5.3 How sequential building blocks work BISTABLES, LATCHES, AND FLIP- FLOPS

2-5.4 Sequential Logic • Suppose we have a sequence of input numbers on X[3:0] that are entered over time that we want to sum up • Possible solution: Route the outputs back to the inputs so we can add the current sum to the input X A0 S0 A1 X[3:0] A2 Z[3:0] S1 9, 3, 2 14,5,2 A3 ‘283 B0 S2 B1 B2 S3 B3

2-5.5 Sequential Logic • Suppose we have a sequence of input numbers on X[3:0] that are entered over time that we want to sum up • Possible solution: Route the outputs back to the inputs so we can add the current sum to the input X • Problem 1: No way to Possible Solution initialize sum X0 A0 S0 Z0 X1 A1 • Problem 2: Outputs can 9, 3, 2 X2 A2 S1 Z1 X3 A3 ‘283 race around to inputs and B0 S2 Z2 be added more than once B1 B2 S3 Z3 per input number B3 Outputs can feedback to inputs and update them sum more than once per input

2-5.6 Sequential Logic • Add logic at outputs to just capture and remember the new sum until we’re ready to input the next number in the sequence This logic should remember (i.e. sequential logic) the sum and only update it when the next number arrives X0 A0 S0 Z0 X1 A1 9, 3, 2 X2 A2 S1 Z1 X3 A3 ‘283 The data can still loop around and add up again B0 S2 Z2 (2+2=4) but if we just B1 hold our output = 2 then B2 S3 Z3 the feedback loop will be B3 broken We remember initial sum of 2 until input 3 arrives at which point we’d capture & remember the sum 5.

2-5.7 Sequence Adder • If X changes once per cycle then Z should also change once per cycle • That is why we will use a register (flip-flops) to ensure the outputs can only update once per cycle 0 C0 Y0 Z0 X0 A0 S0 D Q X1 A1 X2 A2 Y1 Z1 S1 D Q X3 A3 ‘283 Y2 Z2 B0 S2 D Q B1 Y3 Z3 B2 S3 D Q B3 C4 Clear Clock

2-5.8 Sequence Adder • The 0 on Clear will cause Z to be initialized to 0, but then Z can’t change until the next positive edge • That means we will just keep adding 0 + 2 = 2 0 C0 Y0 Z0 X0 A0 S0 D Q time 2 X1 A1 X2 A2 Y1 Z1 S1 D Q Clock X3 A3 2 0 ‘283 Y2 Z2 B0 S2 D Q Clear B1 0 Y3 Z3 B2 S3 D Q B3 2 3 9 X C4 Clear Clock 2 Y Z 0

2-5.9 Sequence Adder • At the edge the flip-flops will sample the D inputs and then remember 2 until the next positive edge • That means we will just keep adding 3 + 2 = 5 0 C0 Y0 Z0 X0 A0 S0 D Q time 3 X1 A1 X2 A2 Y1 Z1 S1 D Q Clock X3 A3 5 2 ‘283 Y2 Z2 B0 S2 D Q Clear B1 2 Y3 Z3 B2 S3 D Q B3 2 3 9 X C4 Clear Clock 2 5 Y Z 0 2

2-5.10 Sequence Adder • Finally, at the positive edge the flip-flops will sample the D inputs and then remember 14 0 C0 Y0 Z0 X0 A0 S0 D Q time X1 A1 X2 A2 Y1 Z1 S1 D Q Clock X3 A3 14 ‘283 Y2 Z2 B0 S2 D Q Clear B1 Y3 Z3 B2 S3 D Q B3 2 3 9 X C4 Clear Clock 2 5 14 Y Z 0 2 5 14

2-5.11 Sequential Logic • But how do flip-flops work? • Our first goal will be to design a circuit that can remember one bit of information • Easiest approach… • But how do you change the input? – A signal should only have one driver

2-5.12 SET/RESET BISTABLES

2-5.13 RS (or SR) Bistable • Terminology – Set = Force output to 1 S Q SR Bistable – Reset = Force output to 0 Q’ R • Set/Reset Bistable Circuit – A circuit that can set or reset its output… – …but then can remember its current output value once the inputs are removed on off

2-5.14 RS (SR) Bistable • Cross-Connected NOR R Q gates (outputs feed back to inputs) • When Set = 1, Q should Q ’ S be forced to 1 • When Reset = 1, Q should be forced to 0 • When neither are 1, Q should remain at its present value

2-5.15 RS (SR) Bistable Always start your analysis from the output Q and cycle it around the loop 2 0 NOR Q’ = Q Q ’ S R Q 0 Q R Q’ Q 0 0 1 1 0 Q and Q’ 0 1 feed back Q 1 1 Q ’ S Q’ 0 2 0 NOR Q = Q ’ 3 Process continues, outputs are remembered

2-5.16 RS (SR) Bistable 3 0 NOR 0 = 1 Q ’ S R Q 0 1 R Q’ Q 0 ’ Q 0 0 Q 0 2 0 feeds 0 1 0 back 0 1 Q 1 1 Q ’ S 0 1 1 NOR 1 anything = 0

2-5.17 RS (SR) Bistable 1 NOR 1 anything = 0 Q ’ S R Q 1 0 R Q’ Q 0 ’ Q 0 0 Q 0 1 0 1 0 0 1 0 1 2 0 feeds Q back 1 1 Q ’ 0 S 1 0 3 0 NOR 0 = 1

2-5.18 RS (SR) Bistable 1 NOR 1 anything = 0 Q ’ S R Q 1 0 R Q’ Q 0 ’ Q 0 0 Q 0 1 0 1 0 0 1 0 1 0 feeds Q back 1 1 Q ’ S 0 1 1 1 NOR anything = •1,1 combination violates the Q, Q’ 0 relationship

2-5.19 RS (SR) Bistable Q ’ 0 S R Q 1 0 R Q 0 ’ Q 0 0 Q 0 1 0 1 0 0 1 0 1 0 feeds back 1 1 0 0 Q ’ (illegal) (illegal) S 0 0 1 •1,1 combination violates the Q, Q’ relationship •It cannot be “remembered”…meaning as soon as R or S goes to 0 then it will set and reset; if R and S goto 0 at the same instant, then we will have unpredictable behavior

2-5.20 Another Waveform • Waveform for an SR bistable with active-hi inputs (cross-connected NOR gates) S R Q Q ’

2-5.21 Criteria for a Bistable 1. Able to independently set (preset) => Force Q=1 2. Able to independently reset (clear) => Force Q=0 3. Able to remember (hold) => Q = Q 0

2-5.22 Exercises • Complete the waveforms below for an RS bistable with active hi inputs S S R R Q Q Q ’ Q ’

2-5.23 A problem with bistables MOTIVATION FOR LATCHES

2-5.24 Problem w/ Bistables • Bistables will remember Start_of_Sequence input values whether A 0 we want them to or not X A 1 F R Q A 2 O A<B A 3 RS • Imagine we connect the Bistable B 0 Q ’ S 10 O A>B 74LS85 B 1 Set input to the output B 2 B 3 O A=B 0 of a comparator to I A<B 0 I A>B 1 I A=B check if any number in a sequence is > 10 and then remember that

2-5.25 Problem w/ Bistables • When inputs change in a Start_of_Sequence combinational circuit, the outputs may transition back A 0 X A 1 F and forth between 1 and 0 R Q A 2 O A<B A 3 RS Bistable • This is called a “glitch” and B 0 Q ’ S 10 O A>B 74LS85 B 1 B 2 is caused due to the B 3 O A=B 0 I A<B propagation delay of the 0 I A>B 1 I A=B combinational logic

2-5.26 Problem w/ Bistables • Suppose we get a Start_of_Sequence sequence: 2,6,7 A 0 X • At the end Q should still A 1 F R Q A 2 O A<B A 3 RS = 0 since no numbers > Bistable B 0 Q ’ S 10 O A>B 74LS85 B 1 10 B 2 B 3 O A=B 0 I A<B • However, if when the 0 I A>B 1 I A=B inputs change a small glitch occurs on A>B, 2 6 7 X the bistable will O A>B remember that and set Q Q = 1 Glitch causes Q to be set

2-5.27 Problem w/ Bistables • Output should have Start_of_Sequence been 0 at end of A 0 sequence X A 1 F R Q A 2 O A<B A 3 RS • Problem: Glitch was Bistable B 0 Q ’ S 10 O A>B 74LS85 B 1 remembered B 2 B 3 O A=B 0 I A<B • Need some way to 0 I A>B 1 I A=B ignore inputs until they are stable and valid 2 6 7 X O A>B Q Glitch causes Q to be set

2-5.28 Clock Signals • A clock signal is an alternating sequence of 1’s and 0’s • It can be used to help ignore the inputs of a bistable when there might be glitches or other invalid values • Idea: – When clock is 0, ignore inputs – When clock is 1, respond to inputs Sample Clock Signal 1 1 1 1 1 1 f = 1 kHz 0 0 0 0 0 0 t = 0 ms 1 ms 2 ms 3 ms 4 ms 5 ms

2-5.29 Latches • Latches are bistables that include a new clock input • The clock input will tell the latch when to ignore the inputs (when C=0) and when to respond to them (when C=1) RS Bistable R Internal R Q RS Latch C Q ’ S S Internal

2-5.30 Latches RS Latch RS Latch (C=0) (C=1) 0 R R R Q Q Q 0 1 C C Q ’ 0 S Q ’ Q ’ S S C=0 causes S=R=0 and thus C=1 allows S,R to pass and Q and Q ’ remain unchanged thus Q and Q ’ are set, reset or remain unchanged based on those inputs

2-5.31 Latches • Rule – When clock = 0, inputs don’t matter, outputs remain the same – When clock = 1, inputs pass to the inner bistable and the outputs change based on those inputs

2-5.32 SR-Latch • When C = 0, Q holds (remembers) its value • When C = 1, Q responds as a normal SR-bistable Q ’ CLK S R Q S Q Q 0 ’ 0 x x Q 0 Q 0 ’ 1 0 0 Q 0 C 1 1 0 1 0 Q’ R 1 0 1 0 1 1 1 1 illegal

2-5.33 SR-Latch Q ’ CLK S R Q S Q Q 0 ’ 0 x x Q 0 Q 0 ’ 1 0 0 Q 0 C 1 1 0 1 0 Q’ R 1 0 1 0 1 1 1 1 illegal CLK S S=1,R=0 causes Q=1 S=1,R=0 R causes Q=1 S=0,R=1 causes Q=0 Q When C=0, Q holds its value