Sequential Logic Design Process Control Flaxer Eli - Process - - PDF document

Flaxer Eli - Process Control

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Chapter 2 Process Control

Sequential Logic Design

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Logic Devices

• Logic devices divide into two major types:
• Combinational Logic

– Current output depends on current input only – Gates, decoders, multiplexers, ALUs

• Sequential Logic

– Current output depends on past inputs as well as current input – Thus has a memory (usually called the state) – Latches, flip-flops, state machines, counters, shift registers

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Sequential Logic Definitions

• Clock - the master timing element behind the state changes of

most sequential circuits.

– a clock signal is active high if the state changes occur at the rising edge – and active low if state changes occur at the falling edge.

• Clock Period - time between successive transitions in the

same direction.

• Clock Frequency - reciprocal of the clock period.
• Duty Cycle - the percentage of time that a clock is at its

assertion level.

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Period tH tL State change

Active High

Period tH tL State change

Active Low

Duty Cycle = tL/Period Frequency = 1/Period

Clock Characteristics

Duty Cycle = tH/Period

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What Are Latches and Flip-flops?

• Common feedback sequential circuits
• Latch

– Single-bit storage (memory) – Changes state at any time due to input change

• Flip-flop

– Also single-bit storage – Changes state ONLY when a clock edge or pulse is applied

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Types of Latches and Flip-flops

• Latches

– S-R Latch – S-R Latch with Enable – D Latch

• Flip-flops

– Edge-Triggered D Flip-Flop – Edge-Triggered S-R Flip-Flop – Edge-Triggered J-K Flip-Flop – T Flip-Flop

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S-R Latch

S R Q /Q 1 1 1 1

Last Q

1

Last /Q

1 S R Q /Q S R Q Q Schematic Symbol Hold Reset Set ILLEGAL Function Table Qa /Qa Set Reset Consider: Timing Diagram Propagation delay Minimum pulse width Oscillation

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D Flip-Flop

D C Q Q C D Q /Q 1 1 1 X 1 Last Q

1

Last /Q Store a data bit, not set/reset “Transparent latch” No illegal operation problem Setup and Hold time D C Q /Q R Q Q C D C S

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Positive-Edge-Triggered D Flip-Flop

D >CLK Q Q D CLK Q /Q 1 X X 1 1 Last Q Last Q

1

Last /Q Last /Q Q’ S R Q Q S R Q Q S R Q Q Q C D S R B A

C = 0 C = 1 D = 0 D = 1 D = 0 D = 1 B 1 1 S 1 1 1 R 1 1 1 A 1 1 Q N .C. N .C. 1 Q’ N .C. N .C. 1

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Negative-Edge-Triggered D Flip-Flop

D CLK Q /Q 1 X X 1 1 Last Q Last Q

1

Last /Q Last /Q D >CLK Q Q

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Edge-Triggered J-K Flip-Flop

J K Q Q >CLK Q D >CLK Q Q /Q CLK J K C Q /Q J X X 1 1

Last Q Last Q

Last Q 1 Last /Q

Last /Q

Last /Q Last /Q 1 Last Q K X X 1 1 1

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T (toggle) Flip-Flop

• A T flip-flop changes state on every clock tick.
• Possible circuit designs

– T without enable

D >CLK Q Q C Q /Q J K Q Q >CLK 1 C Q /Q J K Q Q >CLK T C Q /Q

T with enable T CLK Q

/Q

1 X X 1

Q

/Q Q Q /Q Q /Q /Q

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Flip-Flop

J K Q Q >CLK D >CLK Q Q S R Q Q >CLK T >CLK Q Q D F.F. SR F.F. T F.F. JK F.F.