Sequential Circuits (2) Prof. Usagi Recap: Combinational v.s. - - PowerPoint PPT Presentation

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Sequential Circuits (2) Prof. Usagi Recap: Combinational v.s. - - PowerPoint PPT Presentation

Feb 01, 2023 107 likes •634 views

Sequential Circuits (2) Prof. Usagi Recap: Combinational v.s. sequential logic Combinational logic The output is a pure function of its current inputs The output doesnt change regardless how many times the logic is triggered

slide-1
SLIDE 1

Sequential Circuits (2)

  • Prof. Usagi
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SLIDE 2
  • Combinational logic
  • The output is a pure function of its current inputs
  • The output doesn’t change regardless how many times the logic is

triggered — Idempotent

  • Sequential logic
  • The output depends on current inputs, previous inputs, their history

2

Recap: Combinational v.s. sequential logic

Sequential circuit has memory!

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SLIDE 3
  • A Combinational logic is the implementation of a

Boolean Algebra function with only Boolean Variables as their inputs

  • A Sequential logic is the implementation of a

Finite-State Machine

3

Recap: Theory behind each

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SLIDE 4
  • SR-latch
  • S = 1 sets Q = 1
  • R = 1 sets Q = 0
  • Problem: S = 1, R = 1, Q = undefined
  • Level-sensitive SR-latch
  • S, R only become effective when C = 1
  • Problem: avoid the case of signal oscillation, but

cannot avoid the “intensional” 1,1 inputs

  • D-latch
  • SR can never be 11 if the Clk is set appropriately
  • Problem: D single needs to be stably long enough to set the

memory

  • D-flip-flop
  • Only loads the value into memory in the beginning of the rising
  • edge. Values can hold for a complete clock cycle
  • Problem: more gates

4

Recap: 4-different types of bit storage

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SLIDE 5

Positive-edge-triggered D flip-flop

5

Q Clock Data Q

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SLIDE 6
  • Clock -- Pulsing signal for enabling latches; ticks like a clock
  • Synchronous circuit: sequential circuit with a clock
  • Clock period: time between pulse starts
  • Above signal: period = 20 ns
  • Clock cycle: one such time interval
  • Above signal shows 3.5 clock cycles
  • Clock duty cycle: time clock is high
  • 50% in this case
  • Clock frequency: 1/period
  • Above : freq = 1 / 20ns = 50MHz;

6

Recap: Clock signal

0ns 10ns 20ns 30ns 40ns 50ns 60ns 70ns 80ns 90ns

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SLIDE 7
  • From FSM to circuit
  • Canonical forms of FSMs
  • When sequential circuits meets datapath components

7

Outline

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SLIDE 8

Let’s learn how to design sequential circuits!

8

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SLIDE 9

Which is the most likely circuit realization of Life on Mars

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S0 S1 S2

0/0 0/0 1/1 0/0 1/0 (A) input (D)

Combinational Circuit

input

  • utput

(B) 1/0

Combin ational Circuit

input

D Flip- flop D Q CLK

  • utput

Combin ational Circuit

D Flip- flop D Q

  • utput

D Flip- flop D Q CLK

(C)

Combin ational Circuit

D Flip- flop D Q

  • utput

D Flip- flop D Q CLK

Poll close in

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SLIDE 10

Which is the most likely circuit realization of Life on Mars

10

S0 S1 S2

0/0 0/0 1/1 0/0 1/0 (A) input (D)

Combinational Circuit

input

  • utput

(B) 1/0

Combin ational Circuit

input

D Flip- flop D Q CLK

  • utput

Combin ational Circuit

D Flip- flop D Q

  • utput

D Flip- flop D Q CLK

(C)

Combin ational Circuit

D Flip- flop D Q

  • utput

D Flip- flop D Q CLK

We need memory We have 3 states — 2-bit memory We still need input for transition

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SLIDE 11
  • Input Output Relation
  • State Diagram (Transition of states)
  • State minimization (Reduction)
  • Finite state machine partitioning
  • State Assignment (Map states into binary code)
  • Binary code, Gray encoding, One hot encoding, Coding optimization
  • State Table (Truth table of states)
  • Excitation Table (Truth table of FF inputs)
  • K Map, Minimal Expression
  • Logic Diagram

11

Sequential Circuit Design Flow

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SLIDE 12

Life on Mars

12

S0 S1 S2

0/0 0/0 1/0 1/1 0/0 1/0

Current State Next State, Output Input 1 S0 S1, 0 S0, 0 S1 S2, 0 S0, 0 S2 S2, 0 S0, 1

State Diagram State Diagram input

Combin ational Circuit

D Flip- flop D Q

  • utput

D Flip- flop D Q CLK

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SLIDE 13

Life on Mars

13

S0 S1 S2

0/0 0/0 1/0 1/1 0/0 1/0

Current State Next State, Output Input 1 S0 S1, 0 S0, 0 S1 S2, 0 S0, 0 S2 S2, 0 S0, 1

State Diagram State Diagram State Assignment

S0 00 S1 01 S2 10

input

Combin ational Circuit

D Flip- flop D Q

  • utput

D Flip- flop D Q CLK

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SLIDE 14

Life on Mars

14

S0 S1 S2

0/0 0/0 1/0 1/1 0/0 1/0

Current State Next State, Output Input 1 S0 S1, 0 S0, 0 S1 S2, 0 S0, 0 S2 S2, 0 S0, 1

State Diagram State Diagram State Assignment

S0 00 S1 01 S2 10

State Truth Table

State\Input

1 00 01, 0 00, 0 01 10, 0 00, 0 10 10, 0 00, 1

input

Combin ational Circuit

D Flip- flop D Q

  • utput

D Flip- flop D Q CLK

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SLIDE 15
  • Excitation table is basically the truth table describing the

combinational circuit that provides inputs for the flip-flops in the sequential circuit. How many rows are there in the excitation table of Life on Mars?

  • A. 2
  • B. 3
  • C. 4
  • D. 8
  • E. 32

15

Excitation Table

input

Combin ational Circuit

D Flip- flop D Q

  • utput

D Flip- flop D Q CLK

Poll close in

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SLIDE 16
  • Excitation table is basically the truth table describing the

combinational circuit that provides inputs for the flip-flops in the sequential circuit. How many rows are there in the excitation table of Life on Mars?

  • A. 2
  • B. 3
  • C. 4
  • D. 8
  • E. 32

16

Excitation Table

input

Combin ational Circuit

D Flip- flop D Q

  • utput

D Flip- flop D Q CLK

slide-17
SLIDE 17

Life on Mars

17

State Truth Table

State\Input

1 00 01, 0 00, 0 01 10, 0 00, 0 10 10, 0 00, 1

Excitation Table

NextStateOput StateInput

D1 D0 y 000 001 010 011 100 101 110 111

input

Combin ational Circuit

D Flip- flop D Q

  • utput

D Flip- flop D Q CLK 1 1 1 1 X X X X X X

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SLIDE 18

Life on Mars

18

State Truth Table

State\Input

1 00 01, 0 00, 0 01 10, 0 00, 0 10 10, 0 00, 1

Excitation Table

NextStateOput StateInput

D1 D0 y 000 1 001 010 1 011 100 1 101 1 110 X X X 111 X X X

K-Map — D1 0,0 0,1 1,1 1,0 1 D1 = x’Q0+x’Q1 K-Map — D0 0,0 0,1 1,1 1,0 1 D0 = Q0’Q1’x’ K-Map — y 0,0 0,1 1,1 1,0 1 y = Q1’x input

Combin ational Circuit

D Flip- flop D Q

  • utput

D Flip- flop D Q CLK

1 X 1 X 1 X X X X 1

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SLIDE 19

x y

Circuit — Life on Mars

19

D1 = x’Q0+x’Q1 D0 = Q0’Q1’x’ y = Q1’x

D Flip- flop D Q0 D Flip- flop D Q1

Clk input

Combin ational Circuit

D Flip- flop D Q

  • utput

D Flip- flop D Q CLK

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SLIDE 20

Canonical Form: Mealy and Moore Machines

20

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SLIDE 21

Canonical Form: Mealy and Moore Machines

21

C1 C2

y(t) S(t) Clk x(t)

C1 C2

y(t) S(t) Clk x(t) yi(t) = fi(x(t), S(t)) yi(t) = fi(S(t)) Mealy Machine Moore Machine Result only depends on the current state Result depends on both input and the current state

Si Sj

input/output

Si Sj

input

  • utput

Si(t+1) = gi(x(t), S(t)) Si(t+1) = gi(x(t), S(t))

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SLIDE 22
  • Which type of state machine can describe the “Life on Mars”

pattern recognizer of “001”.

  • A. Moore machine
  • B. Mealy machine
  • C. Both
  • D. None

22

Moore or Mealy? — Life on Mars

Poll close in

C1 C2

y(t) Clk x(t) Moore Machine

C1 C2

y(t) S(t) Clk x(t) Mealy Machine

slide-23
SLIDE 23
  • Which type of state machine can describe the “Life on Mars”

pattern recognizer of “001”.

  • A. Moore machine
  • B. Mealy machine
  • C. Both
  • D. None

23

Moore or Mealy? — Life on Mars

C1 C2

y(t) Clk x(t) Moore Machine

C1 C2

y(t) S(t) Clk x(t) Mealy Machine

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SLIDE 24
  • What does state table need to show to design controls of C2 to

implement pattern recognizer “001”?

  • A. (current input x(t), current state S(t) vs. next state, S(t+1))
  • B. (current input, current state vs. current output y(t))
  • C. (current state vs. current output y(t) and next state)
  • D. (current state vs. current output y(t) )
  • E. None of the above

24

Moore machine for Life on Mars

C1 C2

y(t) Clk x(t) Moore Machine

Poll close in

Si Sj

input

  • utput
slide-25
SLIDE 25
  • What does state table need to show to design controls of C2 to

implement pattern recognizer “001”?

  • A. (current input x(t), current state S(t) vs. next state, S(t+1))
  • B. (current input, current state vs. current output y(t))
  • C. (current state vs. current output y(t) and next state)
  • D. (current state vs. current output y(t) )
  • E. None of the above

25

Moore machine for Life on Mars

C1 C2

y(t) Clk x(t) Moore Machine

Si Sj

input

  • utput
slide-26
SLIDE 26

① Identify distinct (Next State, y) pair ② Replace each distinct (Next State, y) pair with distinct new states ③ Insert rows of present state = new states ④ Append each present state with its output y

26

Conversion from Mealy to Moore

Current State Next State Input 1 S0 S1, 0 S0, 0 S1 S2, 0 S0, 0 S2 S2, 0 S0, 1 Current State Next State Output Input 1 S0 S1 S0 S1 S2 S0 S2 S2 S3 S3

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SLIDE 27

① Identify distinct (Next State, y) pair ② Replace each distinct (Next State, y) pair with distinct new states ③ Insert rows of present state = new states ④ Append each present state with its output y

  • For the given Moore machine, what are the

next states with respect to present state S3?

  • A. S2, S3, 1
  • B. S2, S0, 1
  • C. S1, S0, 1
  • D. S1, S0. 0
  • E. None of the above.

27

Conversion from Mealy to Moore

Current State Next State Input 1 S0 S1, 0 S0, 0 S1 S2, 0 S0, 0 S2 S2, 0 S0, 1 Current State Next State Output Input 1 S0 S1 S0 S1 S2 S0 S2 S2 S3 S3

Poll close in

slide-28
SLIDE 28

① Identify distinct (Next State, y) pair ② Replace each distinct (Next State, y) pair with distinct new states ③ Insert rows of present state = new states ④ Append each present state with its output y

  • For the given Moore machine, what are the

next states with respect to present state S3?

  • A. S2, S3, 1
  • B. S2, S0, 1
  • C. S1, S0, 1
  • D. S1, S0, 0
  • E. None of the above.

28

Conversion from Mealy to Moore

Current State Next State Input 1 S0 S1, 0 S0, 0 S1 S2, 0 S0, 0 S2 S2, 0 S0, 1 Current State Next State Output Input 1 S0 S1 S0 S1 S2 S0 S2 S2 S3 S3 S1 S0 1

slide-29
SLIDE 29

① Identify distinct (Next State, y) pair ② Replace each distinct (Next State, y) pair with distinct new states ③ Insert rows of present state = new states ④ Append each present state with its output y

29

Conversion from Mealy to Moore

Current State Next State Input 1 S0 S1, 0 S0, 0 S1 S2, 0 S0, 0 S2 S2, 0 S0, 1 Current State Next State Output Input 1 S0 S1 S0 S1 S2 S0 S2 S2 S3 S3 S1 S0 1

slide-30
SLIDE 30

State tables for C1 and C2

30

C1 C2

y(t) Clk x(t) Moore Machine

Current State Next State Output Input 1 S0 S1 S0 S1 S2 S0 S2 S2 S3 S3 S1 S0 1

00 01 10 11

State y 00 01 10 11 1

C2 C1

CurrentState-Input

D1 D0 000 1 001 010 1 011 100 1 101 1 1 110 1 111

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SLIDE 31

State tables for C1 and C2

31

C1 C2

y(t) Clk x(t) Moore Machine

Current State Next State Output Input 1 S0 S1 S0 S1 S2 S0 S2 S2 S3 S3 S1 S0 1

00 01 10 11

State y 00 01 10 11 1

C2 C1

CurrentState- Input

D1 D0 000 1 001 010 1 011 100 1 101 110 1 111

K-Map — D1 0,0 0,1 1,1 1,0 1 1 1 1 D1 = x’Q1’Q0+Q1Q0’ K-Map — D0 0,0 0,1 1,1 1,0 1 1 1 1 D0 = Q0’Q1’x’ + Q0Q1x’ + Q0’Q1x’ K-Map — y 1 1 1 y = Q0Q1

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SLIDE 32

When sequential circuits meet datapath components (3)

32

slide-33
SLIDE 33

The delay is determined by the “critical path”

33

C0 B0 A0 C1 B1 A1 C2 B2 A2 C3 B3 A3 Cout0 O0 Cout1 O1 Cout2 O2 Cout3 O3 C4 B4 A4 Cout4 O4 Available in the very beginning Only this is available in the beginning

Carry-Ripple Adder

2-gate delay

slide-34
SLIDE 34
  • All “G” and “P” are immediately available (only need to look over Ai and Bi), but “c” are

not (except the c0).

34

CLA (cont.)

A0 B0 A1 B1 A2 B2 A3 B3 O0 O1 O2 C0 Cout

Carry-lookahead Logic C1 C2 C3 G0 P0 G1 P1 G2 P2 G3 P3

O3

FA FA FA FA C1 = G0 + P0 C0 C2 = G1 + P1 C1 Gi = AiBi Pi = Ai XOR Bi C3 = G2 + P2 C2 C4 = G3 + P3 C3 = G1 + P1 (G0 + P0 C0) = G1 + P1G0 + P1P0C0 = G2 + P2 G1 + P2 P1G0 + P2 P1P0C0 = G3 + P3 G2 + P3 P2 G1 + P3 P2 P1G0 + P3 P2 P1P0C0

slide-35
SLIDE 35
  • Size:
  • 32-bit CLA with 4-bit CLAs — requires 8 of 4-bit CLA
  • Each requires 116 for the CLA 4*(4*6+8) for the A+B — 244 gates
  • 1952 transistors
  • 32-bit CRA
  • 1600 transistors
  • Delay
  • 32-bit CLA with 8 4-bit CLAs
  • 2 gates * 8 = 16
  • 32-bit CRA
  • 64 gates

35

CLA v.s. Carry-ripple

Win! Win! Area-Delay Trade-off!

slide-36
SLIDE 36

Serial Adder

36

slide-37
SLIDE 37

The basic idea

37

C1 C2

y(t) S(t) Clk x(t) Mealy Machine

C1 C2

Clk ai Si bi Feed ai and bi and generate si at time i. Where is ci and ci+1? ci ci+1

slide-38
SLIDE 38

Excitation Table of Serial Adder

38

ai bi ci ci+1 si 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1

slide-39
SLIDE 39

Excitation Table of Serial Adder

39

ai bi ci ci+1 si 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1

ai bi si

D Flip- flop D Q

slide-40
SLIDE 40

40

slide-41
SLIDE 41

41

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SLIDE 42

–Rick Warren

"A lie doesn't become truth, wrong doesn't become right and evil doesn't become good, just because it is accepted by a majority."

42

slide-43
SLIDE 43

–Benjamin Franklin

Honesty is the best policy

43

slide-44
SLIDE 44

44

slide-45
SLIDE 45

–William Shakespeare

Better three hours too soon, than one minute too late.

45

slide-46
SLIDE 46

–Sir John Lubbock

In truth, people can generally make time for what they choose to do; it is not really the time but the will that is lacking.

46

slide-47
SLIDE 47

–Prof. Usagi

Don’t over-commit

47

slide-48
SLIDE 48

Midterm

48

10 20 30 40 50 60 70 80 90 100 1 3 5 7 9 11 13 15 17 19 21 23 25 27 29 31 33 35 37 39 41 43 45 47 49 51 53 55 57 59 61 63 65 67

Average: 79

slide-49
SLIDE 49

Weighted Total — what really decides your final grades

49

10 20 30 40 50 60 70 80 90 100 1 3 5 7 9 11 13 15 17 19 21 23 25 27 29 31 33 35 37 39 41 43 45 47 49 51 53 55 57 59 61 63 65 67

A+ A, A- B+, B, B- C+, C, C- Final Exam

We drop: 2 lowest reading quizzes 1 lowest lab 1 lowest assignment 25% attendance

F

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SLIDE 50
  • Lab 4 — due tonight
  • Reading quiz due this Thursday
  • Assignment #4 due next Tuesday — Chapter 4.8-4.9 &

5.2-5.4

  • Lab 5 is up — due next Thursday
  • Start early & plan your time carefully
  • Watch the video and read the instruction BEFORE your session
  • There are links on both course webpage and iLearn lab section
  • Submit through iLearn > Labs
  • Check your grades in iLearn

50

Announcement

slide-51
SLIDE 51

つづく

Electrical Computer Engineering Science

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