ECE 3060 VLSI and Advanced Digital Design Lecture 9 Logical - - PowerPoint PPT Presentation

ECE 3060 VLSI and Advanced Digital Design

Lecture 9 Logical Effort: Asymmetric Gates, Bundles

ECE 3060 Lecture 9–2

More Notation

• It turns out, we do not need to fix p-fets to be twice as

wide as n-fets (See chapter 7)

• Let

be defined as the ratio of p-fet width to n-fet width in an inverter. Then LE can be defined in terms

• f

.

• So far we have defined LE specifically on a per input

basis.

• The text introduces additional terms:
• The logical effort per bundle is the sum of the logical efforts of

related signals

• Example: A signal

and its complement are both inputs to a

• gate. This input bundle is called

.

• Total logical effort is the sum of the logical effort of all inputs to a

gate.

γ γ s s s*

ECE 3060 Lecture 9–3

Asymmetric Gates

• Consider and AOI21:
• Note that input

has lower logical effort (5/3 vs 2) than

• r

. c a b

ECE 3060 Lecture 9–4

Multiplexors

• There are many styles of MUX design. They can be

designed using logic networks, or they can be designed using tri-state devices.

• Consider the inverting MUX shown here:
• What is logical effort per select bundle, data input,

and total logical effort?

ECE 3060 Lecture 9–5

XOR2 Gate

• Consider the two input XOR
• Total logical effort?
• Logical effort/bundle?
• Logical effort/input ( )?

g

ECE 3060 Lecture 9–6

Symmetric XOR3

• Total logical effort?
• Logical effort/bundle?
• Logical effort/input ( )?

g

ECE 3060 Lecture 9–7

Asymmetric XOR3

• Total logical effort?
• Logical effort/bundle?
• Logical effort/input ( )?

g