ECE 3060 VLSI and Advanced Digital Design Lecture 4 Layout Design - - PowerPoint PPT Presentation

ECE 3060 VLSI and Advanced Digital Design

Lecture 4 Layout Design & Tools

ECE 3060 Lecture 3–7

CMOS Layers

• “Standard” n-Well Process
• Active (Diffusion)
• Polysilicon
• Metal 1, Metal 2, Metal3
• Poly Cut (connects metal 1 to polysilicon)
• Active Cut (connects metal 1 to active)
• Via (connects metal 2 to metal 1)
• Overglass Cut (facilitates off-chip connections)
• n Well
• n Select (used with active to create n-type diffusion)
• p Select (used with active to create p-type diffusion)
• p-well, twin tub, etc. use slightly different layers

ECE 3060 Lecture 3–8

Well, Active, and Select Layout

p-select n-select Active Active n- field oxide p+ n+ p- (substrate) Layout Cross section

ECE 3060 Lecture 3–9

Transistor Layout

p-select n-select Active Active n- field oxide p+ n+ p- (substrate) Layout Cross section p-fet n-fet thin oxide

ECE 3060 Lecture 3–10

Wiring and Contact Layout

ECE 3060 Lecture 3–12

Substrate and Well Contacts

• Properties
• Set Well and Substrate Voltages to Vdd and Gnd
• Prevent Forward Biasing and Latch-Up
• Must Be at Least One per Well
• Should Be Placed Regularly

ECE 3060 Lecture 3–13

Design Rules

• Minimum Separation [A]
• Intralayer (all layers)
• Interlayer (active to poly/well/select)
• From Transistor
• Minimum Width (all layers) [B]
• Minimum Overlap [C]
• Past Transistor (poly, active)
• Around Contact Cut (all contacted layers)
• Around Active (well, select)
• Exact Size (contact cuts) [D]

Lambda Rules for TSMC .18u

• Lambda = .09u
• Cadence Virtuoso does NOT use units of

lambda; instead, units of microns (10-6 meters) are used

12 18 3 3

metal 1 metal 2 metal 3 metal 4

6 6 3 1 2.5 2 4 6 3 3 3

Width/Spacing Rules for TSMC .18u

2

3 2 4 1 2 1 2 1 1 2 2

Contact Design Rules for TSMC .18u

Contact 2x2

ECE 3060 Lecture 4–2

Cell Design Principles

• Cell “Floorplanning”
• Separate nFETs and pFETs
• Use One Continuous Well when Possible
• Set Pitch Using Power and Ground Lines
• Run Busses with Metal 1 and Metal 2 Perpendicular
• Route External Signals to Edges of Cell
• DON’T FORGET
• Substrate and Well Contacts
• Select Around All Active

ECE 3060 Lecture 4–3

Layout Example: CMOS Inverter

• Set Pitch (place well and power/ground busses)

ECE 3060 Lecture 4–4

Layout Example: CMOS Inverter

• Add Transistors (active, select, and poly)

ECE 3060 Lecture 4–5

Layout Example: CMOS Inverter

• Make Connections (poly, metal, and cuts)

ECE 3060 Lecture 4–6

Layout Example: CMOS Inverter

• Add Substrate and Well Contacts

ECE 3060 Lecture 4–7

Layout Example: CMOS Inverter

• Add External Wiring and Resize

ECE 3060 Lecture 4–8

Symbolic Layout

• Stick diagrams capture spatial relationships, but

abstract away design rules

• What gate is this?
• Note: sticks are done slightly differently in text.

B A C Gnd Out Vdd

ECE 3060 Lecture 4–9

Design Capture Tools

• HDL & Schematic capture
• Hardware Description Languages (such as VHDL & Verilog) capture

a textual hierarchical description of design at abstraction ranging from gate or even transistor level up to a behavioral description (more later)

• Schematic editors (such as Cadence Composer) capture a

structural, hierarchical graphical representation of the design netlist.

• Layout
• Layout editors (such as Cadence

Virtuoso) capture a hierarchical view

• f the physical geometric aspect of a
• design. The units of hierarchy are

called cells, and have physical extent (size). In general, good design requires that only one cell contain the design info for a particular area

• f the chip

Cell1 Cell2 Instance1 Instance2 Cell2

ECE 3060 Lecture 4–10

Rules Checking

• Complex designs invariably suffer design and design

entry errors. There are a number of tools and method-

• logies to detect and correct.
• Physical Design Rules Checking (DRC) checks for design rule

violations such as minimum spacing etc. DRC checking is complicated by hierarchy and overlap between cells.

• Electrical Rule Checking checks for violations such as shorts

between Vdd and GND, opens, and so on.

• Layout vs Schematic (LVS) checks for a one to one correspondence

between transistor schematic and the layout.

• Formal verification is used to show that the design

satisfies a formal description of what it should do.

• Simulation is used to show that the design is func-

tional on some well selected set of input vectors.

• Timing analysis is used to predict design performance

ECE 3060 Lecture 4–11

Verification

• Two types:
• Simulation based verification
• test vectors
• Formal verification
• mathematical properties
• boolean logic
• Trend: include formal verification in the design
• invariants

ECE 3060 Lecture 4–12

Circuit Extraction

• Circuit extraction extracts a schematic representation
• f a layout, including transistors, wires, and possibly

wire and device resistance and capacitance.

• Circuit extraction is used for LVS, and for spice simu-

lation of layouts

ECE 3060 Lecture 4–13

Cell (datapath) Generators

• Custom layout of a chip is very time consuming and is

justifiable only in very high volume design with critical requirements, or in research.

• A datapath generator is a program designed to para-

metrically create a data path cell (say an ALU cell) which can meet size, pitch, and timing constraints.

ECE 3060 Lecture 4–14

Standard Cell Approach

• Use full custom process, but design to higher level

abstraction

• SSI (NAND, NOR, INV, XOR, Register,...).
• MSI (Decoder, Adder, Comparator,...).
• Datapath (ALU, Shifter, Register file).
• Memory (RAM, ROM, CAM,...).
• Cells are designed at multiples of std pitch
• Cells may be parameterized for power, speed,..
• Design target is netlist of cells which are then placed

and routed using automated tools

ECE 3060 Lecture 4–15

Standard Cell Design

• Cells are designed to abut horizontally.
• Cells are placed and routed automatically
• Wiring channels may have variable # of tracks.