ECE 3060 VLSI and Advanced Digital Design Lecture Datapath2: - - PowerPoint PPT Presentation

ECE 3060 VLSI and Advanced Digital Design

Lecture Datapath2: Registers,Comparators, Shifters, Decoders

ECE 3060 Lecture 16–2

D Latch

basic latch transparent latch loading storing

• ut
• ut

in in circuit schematic

• ut

in

load / store

ECE 3060 Lecture 16–3

Single Phase FF (Register)

• PROBLEM: transparent latch can cause “oscillations”

when used in a sequential circuit

• SOLUTION: a master-slave flip-flop (register cell)

transparent latch transparent latch in

• ut

clock master slave clock master slave loading storing loading storing storing loading storing loading

ECE 3060 Lecture 16–4

Delay and Clock Overlap

master slave transparent latch transparent latch in

• ut

clk clk clk clk

ideal

clk clk

with delay clock

• verlap

ECE 3060 Lecture 16–5

Non-overlapping Two Phase Clocks

• Advantages over Single-Phase Clocking
• No Potential for Latches to be Transparent Simultaneously
• Resistant to Delays in Circuit

transparent latch transparent latch in

• ut

master slave

φ1 φ2 φ1 φ2

non-overlap periods

ECE 3060 Lecture 16–6

Register Layout

• Data and control flows left to right
• Register is formed by tiling in the vertical direction
• Attempt is to minimize vertical pitch

LD LD Vdd Gnd LD LD

D

Q Q

ECE 3060 Lecture 16–7

Alternate Layout

• Data still flows left to right, but control is vertical
• Register is tiled vertically
• Horizontal pitch is minimized

Vdd Vdd Gnd

D

LD LD Q Q

ECE 3060 Lecture 16–8

Points to Note

• Vdd and Gnd must be sized to carry necessary current

(1–2 mA/micron)

• Cells may be flipped vertically to share Vdd and Gnd
• Well contacts not shown
• Vdd and Gnd inter-digitated

Vdd Gnd

ECE 3060 Lecture 16–9

Comparator Circuits

• Comparator may be implemented using adder/subtrac-

tor, or:

• Pass gate implementation:
• Note the use of nfets to pass ‘1’! This saves significant

area, at a slight penalty in speed and sensitivity to noise.

A0 B0 A1 B1

Vdd Vdd

A B =

ECE 3060 Lecture 16–10

Comparator (cont.)

• Transmission gates could also be used.
• Signal must be restored every 3-4 stages.
• Note the use of feedback at the output to sharpen the
• utput transition, and bring it all the way to the upper

rail (Vdd)

ECE 3060 Lecture 16–11

Multi-bit Shifters

• There are several types of multibit (barrel) shifters
• An arithmetic right shift by

is multiplication by

• An arithmetic left shift by

is multiplication by

• A logical shift by

ignores sign

• Rotate by
• There are several implementation
• Transmission gate (

needs decoder)

• Multiplexor (

no decoder needed)

k 2 k

–

k 2k k A O n2 ( ) = A n n log =

ECE 3060 Lecture 16–12

T-gate Shifter

O0 O1 O2 O3 I6 I5 I4 I3:0 S3 S2 S1 S0

ECE 3060 Lecture 16–14

Cell Layout

• Cell layout requires consideration of signal flow

Overlap Needed No Overlap Needed 2x2 Tiling

ECE 3060 Lecture 16–13

Shifter Operation

• By multiplexing the inputs to the shifter, one can spec-

ify the shifter operation

• Logical right shift
• Arithmetic right shift
• Logical left shift (complement

)

• Rotate left (complement

)

• Rotate right

000D3:0 D3D3D3D3:0 D3:0000 k D3:0D3:1 k D2:0D3:0

ECE 3060 Lecture 16–15

Multiplexor Shifter

• Basic idea: rows of 2x1 muxes which shift by
• Does not need decoder, but wiring is expensive
• May use inverting mux to simplify implementation

2k Shift by 1 Shift by 2 Shift by 4

I7 I6 I5 I4 I3 I2 I1 I0

ECE 3060 Lecture 16–16

Predecoder Scheme

• Cascaded stages of 2-4

input NAND/NOR gates

• Layout is PLA like tiles
• Vertical pitch is deter-

mined by rightmost column

• Branching effort is reduced

for some inputs