ECE 3060 VLSI and Advanced Digital Design Lecture Datapath2: Registers,Comparators, Shifters, Decoders
D Latch basic latch in out in out loading storing transparent latch in out load / store circuit schematic ECE 3060 Lecture 16–2
Single Phase FF (Register) • PROBLEM: transparent latch can cause “oscillations” when used in a sequential circuit • SOLUTION: a master-slave flip-flop (register cell) master slave transparent transparent out in latch latch clock clock master loading storing loading storing slave storing loading storing loading ECE 3060 Lecture 16–3
Delay and Clock Overlap master slave transparent transparent out in latch latch clk clk clk ideal clk clk clock with delay overlap clk ECE 3060 Lecture 16–4
Non-overlapping Two Phase Clocks master slave transparent transparent out in latch latch φ 1 φ 2 φ 1 non-overlap periods φ 2 • Advantages over Single-Phase Clocking • No Potential for Latches to be Transparent Simultaneously • Resistant to Delays in Circuit ECE 3060 Lecture 16–5
Register Layout LD LD V dd Q D Q Gnd LD LD • Data and control flows left to right • Register is formed by tiling in the vertical direction • Attempt is to minimize vertical pitch ECE 3060 Lecture 16–6
Alternate Layout V dd Q D Q Gnd V dd LD LD • Data still flows left to right, but control is vertical • Register is tiled vertically • Horizontal pitch is minimized ECE 3060 Lecture 16–7
Points to Note • Vdd and Gnd must be sized to carry necessary current (1–2 mA/micron) • Cells may be flipped vertically to share Vdd and Gnd • Well contacts not shown • Vdd and Gnd inter-digitated Vdd Gnd ECE 3060 Lecture 16–8
Comparator Circuits • Comparator may be implemented using adder/subtrac- tor, or: • Pass gate implementation: Vdd Vdd = A B A 0 B 0 A 1 B 1 • Note the use of nfets to pass ‘1’! This saves significant area, at a slight penalty in speed and sensitivity to noise. ECE 3060 Lecture 16–9
Comparator (cont.) • Transmission gates could also be used. • Signal must be restored every 3-4 stages. • Note the use of feedback at the output to sharpen the output transition, and bring it all the way to the upper rail (Vdd) ECE 3060 Lecture 16–10
Multi-bit Shifters • There are several types of multibit (barrel) shifters – 2 k • An arithmetic right shift by is multiplication by k 2 k • An arithmetic left shift by is multiplication by k • A logical shift by ignores sign k • Rotate by • There are several implementation O n 2 = ( ) • Transmission gate ( needs decoder) A = log • Multiplexor ( no decoder needed) A n n ECE 3060 Lecture 16–11
T-gate Shifter S 3 S 2 S 0 S 1 O 3 I 6 O 2 I 5 O 1 I 4 O 0 I 3:0 ECE 3060 Lecture 16–12
Cell Layout • Cell layout requires consideration of signal flow No Overlap Overlap Needed Needed 2x2 Tiling ECE 3060 Lecture 16–14
Shifter Operation • By multiplexing the inputs to the shifter, one can spec- ify the shifter operation 000 D 3:0 • Logical right shift • Arithmetic right shift D 3 D 3 D 3 D 3:0 D 3:0 000 • Logical left shift (complement ) k • Rotate left (complement ) D 3:0 D 3:1 k • Rotate right D 2:0 D 3:0 ECE 3060 Lecture 16–13
Multiplexor Shifter • Basic idea: rows of 2x1 muxes which shift by 2 k I 7 I 6 I 5 I 4 I 3 I 2 I 1 I 0 Shift by 1 0 Shift by 2 Shift by 4 • Does not need decoder, but wiring is expensive • May use inverting mux to simplify implementation ECE 3060 Lecture 16–15
Predecoder Scheme • Cascaded stages of 2-4 input NAND/NOR gates • Layout is PLA like tiles • Vertical pitch is deter- mined by rightmost column • Branching effort is reduced for some inputs ECE 3060 Lecture 16–16
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