ECE 3060 VLSI and Advanced Digital Design Lecture 1 Introduction
You will need: • Text: Modern VLSI Design Wolf • Text: Logical Effort Sutherland et. al. • Reference: Your previous digital design text • Colored pencils • red • green • brown • blue • purple or cyan • To take good notes ECE 3060 Lecture 1–2
Course Objectives • Fundamentals of VLSI • CMOS technology • layout • performance (timing and power) • design styles • module designs (e.g. adders, faster adders, barrel shifters,... • Advanced issues in digital design • combinational logic minimization • sequential logic minimization • clocking • synchronization and asynchronous design • testing ECE 3060 Lecture 1–3
A Word on Academic Integrity • Where is “the line” in a lab and design course? • Do: • Discuss lab problems with your colleagues • Discuss homeworks with your colleagues • Discuss design tools issues with your colleagues • Don’t: • Work “together” to solve a homework set • Turn in identical papers • “Share” layouts, simulations, etc. • Violations of the Honor Code will be referred to the Dean of Students for resolution. ECE 3060 Lecture 1–4
VLSI is Complexity • Question: How do we deal with devices with tens of millions of components? ECE 3060 Lecture 1–5
Intel Microprocessors • Size is scaled so transistor size is constant • ’82: 134K, ’85: 275K, ’89:1.2M, ’93: 3.1M, ’95: 5.5M ECE 3060 Lecture 1–6
VLSI is Complexity • Answer: • Abstraction and Hierarchy • Simulation and Verification • Regularity and Modularity ECE 3060 Lecture 1–7
Abstraction and Simulation Requirements Behavioral Simulation Functional Design Register Transfer RTL Simulation Level Design Validation Logic/Timing Simulation Logic Design Verification Fault Simulation Circuit Design Timing Simulation Circuit Analysis Design Rule Checking Physical Design Electrical Rule Checking Description for Manufacture • Simulation is faster at higher levels of abstraction ECE 3060 Lecture 1–9
Design Representations STRUCTURAL BEHAVIORAL algorithms processors register transfers registers gates Boolean expressions transistors transfer functions cells modules chips boards PHYSICAL [Gajski and Kuhn] • Design is structured around a hierarchy of representa- tions or facets • HDLs can describe distinct aspects of a design at mul- tiple levels of abstraction ECE 3060 Lecture 1–10
Reducing Complexity by Reuse • Regularity means standardize aspects of design to simplify tasks. This Not This • This is regularity in pitch and function. • Modularity means design cells so they may be used in multiple places (maximize reuse). ECE 3060 Lecture 1–11
Raising the Level of Abstraction at Which the Designer Spends the Most Time • Design using ASCII based Hardware Description Lan- guages (Verilog, VHDL) • Design at the logic level (Boolean) and automate translation to the gate level and then to layout • Computer-Aided Design: • Logic Synthesis (generate gate-level description from logic descr.) • Place & Route (place the gates and connect them with wires) • Advantage: faster design time; Disadvantage: greater area, delay • Use predesigned components • Multipliers, Adders • Processors, Ethernet hardware • Move more functionality to software ECE 3060 Lecture 1–12
VLSI Building Blocks • Transistors • Basic Element of all VLSI Structures • Metal-Oxide-Semiconductor Field-Effect Transistor • n-channel and p-channel MOSFETs • Terminals: Gate, Drain, Source, (Bulk) • Wires • Used to Connect Transistors • Constructed from Metal and Polysilicon • Metal Wires: low resistivity, long and short wires, 2-3+ layers • Polysilicon Wires: higher resistivity, short wires, MOSFET gates, 1- 2 layers ECE 3060 Lecture 1–13
The MOSFET Drain Gate Source Gate Drain Source Current Current Flow Flow Cross Section Schematic Icon • Terminals • Gate: controls current flow between drain and source • Drain/Source: form current-conducting path • (Bulk) • Functionality • Voltage-Controlled Current Source • Simple Model = Switch ECE 3060 Lecture 1–14
p- and n-channel MOSFETs V d V s V g V g pFET nFET V s V d nFET pFET V g = 0 : Switch is open closed V g = 1 : Switch is closed open Switch can pull down pull up V dd Source connects to Gnd ECE 3060 Lecture 1–15
Why use both p- and n-channel MOSFETs? • When pulling down to ground: • nFET: V ds = 0V • pFET: V ds = 0.7V (exact value depends on technology, but is always greater than zero) • When pulling up to Vdd: • nFET: V ds = 0.7V (exact value depends on technology, but is always greater than zero) • pFET: V ds = 0V ECE 3060 Lecture 1–16
Complementary MOS (CMOS) • Most common VLSI technology • Uses both n- and p-channel FETs • Pulldown (to Gnd) networks of nFETs V dd • Pull-up (to ) networks of pFETs • Advantages over other technologies • Lower static power dissipation • Design flexibility due to two device types • Compact • Reasonably high speed ECE 3060 Lecture 1–17
Circuit Example: The CMOS Inverter input output 0 1 1 0 ECE 3060 Lecture 1–18
Complementary Networks • Basic idea: connect F to 1 when true, and to 0 when false 1 Pullup F X ( ) X F Pulldn F X ( ) 0 • Pullups are p-FETS and pulldowns are n-FETS ECE 3060 Lecture 1–19
Example: NAND Gate • Function F = A B ⋅ = A + B • Pull-Up Network A B = + F A B • F • OR is parallel • Pull-Down Network A = ⋅ F A B • B • AND is serie ECE 3060 Lecture 1–20
Recommend
More recommend
