Systems Sequential Elements Shankar Balachandran* Associate - - PowerPoint PPT Presentation

Shankar Balachandran* Associate Professor, CSE Department Indian Institute of Technology Madras

*Currently a Visiting Professor at IIT Bombay

Digital Circuits and Systems

Spring 2015 Week 4 Module 18

Sequential Elements

Motivation

 Hotels have housekeeping

 When the guest leaves the room, can request for housekeeping

 I am going out now. Please clean up the room before I return.

 Guest can press a button (SET) saying room needs

housekeeping and leave the room.

 A light on the outside turns ON indicating that the room needs

cleaning.

 Housekeeping staff who comes around can see a light

when it turns on and can clean the room

 The staff should remember to turn off the light

 Don’t want a room to be cleaned again and again on the same

day

 Should RESET

Sequential Elements 2

Memory element Light Housekeeping Request Reset Set On Off



Sequential Logic Elements 4

Sequential Logic Circuits

 In a sequential circuit steady state outputs are a function

• f the current inputs and past inputs; i.e., the circuit has

memory

 Feedback in the logic paths.  The state of the circuit is the state of the memory

A B

Simplest Memory Element

Sequential Logic Elements 6

Latches and Flip-Flops

 Latches and flip-flops are the basic building blocks of

sequential circuits

 Bistable devices – 0 state and 1 state.

Reset Set Q

Memory Element with NOR Gates

Sequential Logic Elements 8

SR Latch

 The most basic sequential circuit is an SR latch (the term

latch may be used to indicate the device operates in a direct mode – but the term is not always used this way)

 S = set (input); R = reset (input); Q = current state of the

latch (output); = complement of current latch state (output); note – no clock signal  SR latch is asynchronous.

 NOR implementation of an SR latch:

Q

S R Q a Q b 1 1 1 1 0/1 1/0 1 1 (a) Circuit (b) Truth table Time 1 1 1 1 R S Q a Q b Q

a

Q

b

? ? (c) Timing diagram R S t

1

t

2

t

3

t

4

t

5

t

6

t

7

t

8

t

9

t

10

(no change)

Sequential Logic Elements 10

NOR SR Latch – Characteristic Table

 Given the current state and inputs to a latch, what is the next state.

Typically, symbols Q, Qn-1,Qt, etc. are used to denote the current state, and correspondingly , Q*, Qn, Qt+1, etc. denote the next state. S R Q* 0 0 Q 0 1 1 0 1 1 1

Undefined (0 0)

Sequential Logic Elements 11

NAND SR Latch

S R Q* 0 0

Undefined (1 1)

0 1 1 0 1 1 1 Q

Characteristic Table

Gated SR Latch

Sequential Elements 12

Clk S R Q(t+1) 1 Q(t) 1 1 1 1 1 1 1 1

Undefined

X X Q

 Still have problems with 11 inputs to SR latch.

S R Clk Q Q

Gated SR Latch with NAND Gates

CLK S R Q(t+1) 1 Q(t) 1 1 1 1 1 1 1 1

Undefined

X X Q

 Still have problems with 11 inputs to SR latch – one solution is to

define the condition away: never allow both inputs to the SR to have the same value.

Sequential Logic Elements 14

Gated D latch

 D (data) latch or D flip-flop does not allow both inputs to an SR

latch to have the same value.

 A register is an array of D latches or flip-flops which share a

common gate/clock – this is a fundamental building block for computer design. G D Q* Q* 1 0 1 1 1 1 0 X Q Q

Characteristic Table

End of Week 4: Module 18

Thank You

Sequential Elements 15