Systems Sequential Elements Shankar Balachandran* Associate - PowerPoint PPT Presentation

Spring 2015 Week 4 Module 18 Digital Circuits and Systems Sequential Elements Shankar Balachandran* Associate Professor, CSE Department Indian Institute of Technology Madras *Currently a Visiting Professor at IIT Bombay

Motivation  Hotels have housekeeping  When the guest leaves the room, can request for housekeeping  I am going out now. Please clean up the room before I return.  Guest can press a button (SET) saying room needs housekeeping and leave the room.  A light on the outside turns ON indicating that the room needs cleaning.  Housekeeping staff who comes around can see a light when it turns on and can clean the room  The staff should remember to turn off the light  Don’t want a room to be cleaned again and again on the same day  Should RESET Sequential Elements 2

Set Housekeeping  On Off Memory Request Light element Reset

Sequential Logic Circuits  In a sequential circuit steady state outputs are a function of the current inputs and past inputs; i.e., the circuit has memory  Feedback in the logic paths.  The state of the circuit is the state of the memory Sequential Logic Elements 4

Simplest Memory Element A B

Latches and Flip-Flops  Latches and flip-flops are the basic building blocks of sequential circuits  Bistable devices – 0 state and 1 state. Sequential Logic Elements 6

Memory Element with NOR Gates Reset Set Q

SR Latch  The most basic sequential circuit is an SR latch (the term latch may be used to indicate the device operates in a direct mode – but the term is not always used this way)  S = set (input); R = reset (input); Q = current state of the latch (output); = complement of current latch state Q (output); note – no clock signal  SR latch is asynchronous .  NOR implementation of an SR latch: Sequential Logic Elements 8

Q a Q b S R R Q a (no change) 0 0 0/1 1/0 0 1 0 1 1 0 1 0 1 1 0 0 Q b S (a) Circuit (b) Truth table t t t t t t t t t t 1 2 3 4 5 6 7 8 9 10 1 R 0 1 S 0 1 Q a ? 0 1 Q b ? 0 Time (c) Timing diagram

NOR SR Latch – Characteristic Table  Given the current state and inputs to a latch, what is the next state. Typically, symbols Q, Q n-1 ,Q t , etc. are used to denote the current state, and correspondingly , Q * , Q n , Q t+1 , etc. denote the next state. S R Q* 0 0 Q 0 1 0 1 0 1 1 1 Undefined (0 0) Sequential Logic Elements 10

NAND SR Latch S R Q* 0 0 Undefined (1 1) 0 1 0 1 0 1 Characteristic Table 1 1 Q Sequential Logic Elements 11

Gated SR Latch Clk S R Q(t+1) 1 0 0 Q(t) 1 0 1 0 1 1 0 1 1 1 1 Undefined 0 X X Q  Still have problems with 11 inputs to SR latch. Sequential Elements 12

Gated SR Latch with NAND Gates CLK S R Q(t+1) S 1 0 0 Q(t) Q 1 0 1 0 Clk 1 1 0 1 1 1 1 Undefined Q 0 X X Q R  Still have problems with 11 inputs to SR latch – one solution is to define the condition away: never allow both inputs to the SR to have the same value.

Gated D latch  D (data) latch or D flip-flop does not allow both inputs to an SR latch to have the same value. G D Q* Q* 1 0 0 1 1 1 1 0 Characteristic Table 0 X Q Q  A register is an array of D latches or flip-flops which share a common gate/clock – this is a fundamental building block for computer design. Sequential Logic Elements 14

End of Week 4: Module 18 Thank You Sequential Elements 15