ECE 3060 VLSI and Advanced Digital Design Lecture 13 Datapath1: ALUs and Adders
Datapath Floorplan • Busses run through cells • Pitch is matched • Vdd and Gnd are run horizontally • Current draw on Vdd and Gnd is spread in time to minimize spiking ECE 3060 Datapath1–2
Example Chip Floorplan ECE 3060 Datapath1–3
Transmission Gate Mux I0 I0 I1 I1 Out I2 I2 I3 I3 S1 S1 S0 S0 • Note: Two t-gates in series do not need the internal connection between p-fet and n-fet S1 S1 S0 S0 ECE 3060 Datapath1–4
Function Block • 4x1 multiplexor can implement any function of two variables A B S 4 F • Simply place the truth table for F on the inputs of the mux. • The operands A and B will select the correct value of the function ECE 3060 Datapath1–5
Adder Cells SUM = A ⊕ B ⊕ C • = C AB ( + AB ) + C AB ( + AB ) CARRY = AB + AC + BC • = AB + C A ( + B ) • Above equations may be implemented as complex gates • These equations may be manipulated to yield: SUM = + ( + + ) CARRY ABC A B C ECE 3060 Datapath1–6
Adder Layout ECE 3060 Datapath1–7
Transmission Gate Full Adder • Truth Table 2x1 Mux A B C Sum Carry 0 0 0 0 0 0 0 1 1 0 0 1 0 1 0 2x1 Mux 0 1 1 0 1 1 0 0 1 0 1 0 1 0 1 1 1 0 0 1 1 1 1 1 1 • When , , and . A ⊕ B = 0 SUM = C Carry = B • When , , and . = 1 SUM = Carry = A ⊕ B C C • Using the 6T XOR, this full adder uses 18T. ECE 3060 Datapath1–8
Transmission Gate Adder ECE 3060 Datapath1–9
Carry Lookahead • Ripple carry delays may be unacceptable for wider n bit adders C in C out Delay is proportional to n • There are many, many schemes for speeding up the calculation of carry bits. • “Traditional CLA” designs are based upon calculating the carry bits in parallel (this takes time O ( log n ) because the fanin to the CLA function is ) O n ( ) • Other designs are based on speeding up the ripple. ECE 3060 Datapath1–10
Carry Propagate and Generate • A carry out is generated from bit position , C i i + 1 when both and are ‘1’ i.e. = A i B i G i A i B i • A carry in is propagated to the carry out at bit position when either or is ‘1’ (if both are ‘1’ will i A i B i G i cover) e.g. P i = A i ⊕ B i complex gate (6T) • Thus the carryout, C i = G i + P i C i + 1 ECE 3060 Datapath1–11
Manchester Carry Chain • Propagate and generate sig- nals computed in about two gate delays P i • Active low carry is propa- gated through a chain of P i G i transmission gates C i C i + 1 • The three shaded areas of G i the circuit are mutually P i exclusive, and represent , P i , and . G i P i G i ECE 3060 Datapath1–12
Alternate Implementation • The Manchester carry chain computation may also be implemented with a 2x1 mux. P i C i P i C i + 1 G i P i ECE 3060 Datapath1–13
4-bit Block • Signal propagation through a chain of transmission gates must be restored after about 4 gates G 0 P 0 G 1 P 1 G 2 P 2 G 3 P 3 C 1 C 4 – P 0 P 1 P 2 P 3 C 0 C 1 C 2 C 3 • A block propagate (bypass) circuit may be added to further improve performance on wide adders ECE 3060 Datapath1–14
Carry Select Adder • Calculate each block assuming , and , then mux C in C in the result (4-2x1) A 3:0 B 3:0 A 7:4 B 7:4 A 7:4 B 7:4 C 8 Complex gate S 3:0 S 7:4 ECE 3060 Datapath1–15
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