ECE 3060 VLSI and Advanced Digital Design Lecture 13 Datapath1: - - PowerPoint PPT Presentation

ECE 3060 VLSI and Advanced Digital Design

Lecture 13 Datapath1: ALUs and Adders

ECE 3060 Datapath1–2

Datapath Floorplan

• Busses run through cells
• Pitch is matched
• Vdd and Gnd are run horizontally
• Current draw on Vdd and Gnd is spread in time to minimize spiking

ECE 3060 Datapath1–3

Example Chip Floorplan

ECE 3060 Datapath1–4

Transmission Gate Mux

I0 I1 I2 I3 Out I0 I1 I2 I3

S0 S1 S0 S1 S0 S1 S0 S1

• Note: Two t-gates in

series do not need the internal connection between p-fet and n-fet

ECE 3060 Datapath1–5

Function Block

• 4x1 multiplexor can implement any function of two

variables

• Simply place the truth table for F on the inputs of the

mux.

• The operands A and B will select the correct value of

the function A B F S 4

ECE 3060 Datapath1–6

Adder Cells

• Above equations may be implemented as complex

gates

• These equations may be manipulated to yield:

SUM A B C ⊕ ⊕ = C AB AB + ( ) C AB AB + ( ) + = CARRY AB AC BC + + = AB C A B + ( ) + = SUM ABC A B C + + ( )CARRY + =

ECE 3060 Datapath1–7

Adder Layout

ECE 3060 Datapath1–8

Transmission Gate Full Adder

• Truth Table
• When

, , and .

• When

, , and .

• Using the 6T XOR, this full adder uses 18T.

A B C Sum Carry 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1

2x1 Mux 2x1 Mux

A B ⊕ = SUM C = Carry B = A B ⊕ 1 = SUM C = Carry C =

ECE 3060 Datapath1–9

Transmission Gate Adder

ECE 3060 Datapath1–10

Carry Lookahead

• Ripple carry delays may be unacceptable for wider

bit adders

• There are many, many schemes for speeding up the

calculation of carry bits.

• “Traditional CLA” designs are based upon calculating

the carry bits in parallel (this takes time because the fanin to the CLA function is )

• Other designs are based on speeding up the ripple.

n Cin Cout Delay is proportional to n O n log ( ) O n ( )

ECE 3060 Datapath1–11

Carry Propagate and Generate

• A carry out

is generated from bit position , when both and are ‘1’ i.e.

• A carry in is propagated to the carry out at bit position

when either

• r

is ‘1’ (if both are ‘1’ will cover) e.g.

• Thus the carryout,

Ci

1 +

i Ai Bi Gi AiBi = i Ai Bi Gi Pi Ai Bi ⊕ =

complex gate (6T)

Ci

1 +

Gi PiCi + =

ECE 3060 Datapath1–12

Manchester Carry Chain

• Propagate and generate sig-

nals computed in about two gate delays

• Active low carry is propa-

gated through a chain of transmission gates

• The three shaded areas of

the circuit are mutually exclusive, and represent , , and .

Gi Gi Pi Pi Ci Ci

1 +

Pi

Pi Gi PiGi

ECE 3060 Datapath1–13

Alternate Implementation

• The Manchester carry chain computation may also be

implemented with a 2x1 mux.

Pi Pi Pi Gi Ci Ci

1 +

ECE 3060 Datapath1–14

4-bit Block

• Signal propagation through a chain of transmission

gates must be restored after about 4 gates

• A block propagate (bypass) circuit may be added to

further improve performance on wide adders

G0 G1 G2 G3 P0 P1 P2 P3 C0 C1 C2 C3 C 1

–

C4 P0 P1 P2 P3

ECE 3060 Datapath1–15

Carry Select Adder

• Calculate each block assuming

, and , then mux the result (4-2x1) Cin Cin

Complex gate

A3:0 B3:0 A7:4 B7:4 A7:4 B7:4 S3:0 S7:4 C8