Floating Point Representation and Digital Logic Lecture 11 CS301 - - PowerPoint PPT Presentation

Floating Point Representation and Digital Logic

Lecture 11 CS301

Administrative

• Daily Review of today’s lecture

w Due tomorrow (10/4) at 8am

• Lab #3 due Friday (9/7) 1:29pm
• HW #5 assigned

w Due Monday 10/8 at 5pm

• Program #1 assigned

w Due Thursday, 10/18 at 11:59pm

• Read Appendix C.1-C.3, C.5

Digital Logic

(How do we construct a processor?)

Multi-Million Transistor Chips

Intel Core i7 Extreme Edition - 731 million transistors, 263 mm^2 area

MOS Semiconductor Transistors

P-type silicon: Excess positive charges (electron holes) N-type silicon: Excess negative charges (electrons) Oxide: Insulator Gate: Metal pad In this state, current (electrons) cannot flow between source and drain – switch is OPEN

Silicon Bulk (p-type)

+ + + + + + + + + + + + + + + + + + + + + + +

e- e- e- e- e- e- e- e- e-

+ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +

e- e- e- e- e-

Source

e- e- e- e-

Drain Gate

n-type Si n-type Si Source Wire Gate Wire

Oxide

Drain Wire

MOS Semiconductor Transistors

Silicon Bulk (p-type)

+ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +

e- e- e- e- e-

Source

e- e- e- e-

Drain Gate

n-type Si n-type Si Source Wire Gate Wire

Oxide

+5V

+ + + + + + + + +

e- e- e-

Place a positive charge on the gate wire (gate = +5V) The gate’s positive charge attracts negatively-charged electrons This row of electrons forms a channel connecting the Source and Drain – Current can flow – Switch is CLOSED

Drain Wire

e- e- e- e- e- e- e- e-

Transistors

• Transistors

w Emits 0 or 1 when on

• r off

w Can connect transistors in series

• r parallel to create

larger building blocks called gates

Pull-up pMOS transistor Pull-down nMOS transistor

GND +5V A Z

CMOS Inverter created from two transistors

Digital Logic

• Voltages represent values

w Logically false - 0 w Logically true - 1

• Values are complements or inverses

Gates: Basic Building Blocks:

• Depending on organization of transistors, different

inputs give specific outputs

• Basic gates equivalent to boolean operators

w INVERTER or NOT, ! w AND, && w OR, ||

• Combinational logic

w Outputs based on inputs w No memory A A A A • B B A A + B B

Truth Tables

• Functionality fully

specified by truth table

• n inputs

w n input columns w 2n input rows

• m outputs

w m output columns

A Z 1 1 A B Z 1 1 1 1 1 A B Z 1 1 1 1 1 1 1

NOT AND OR

Combinational Logic

• Gates can be

combined in

w Series w Parallel

• Any combination of

both possible

A B Y Z 1 1 1 1 1 1 1

A A A B Y Z

Other Important Gates

• NAND
• NOR

A B Z 1 1 1 1 1 1 1 A B Z 1 1 1 1 1

A A B B A A + B B

Universal Gates

• Any other gate can be constructed

from some arrangement of universal gates

w Examples: NAND / NOR

• Important because frequently less

expensive to design chips with “homogeneous” gates

Universal Gates
 (NAND)

• NOT

A A AA 1 1 1

A A A

Universal Gates
 (NAND)

• NOT
• AND

A A AA 1 1 1

A A A

A B AB 1 1 1 1 1

Universal Gates
 (NAND)

• NOT
• AND

A A AA 1 1 1 A B AB AB 1 1 1 1 1 1 1 1

A A A A A B B

Universal Gates
 (NAND)

• OR

A B A+B 1 1 1 1 1 1 1

Universal Gates
 (NAND)

• OR

A B A+B AB 1 1 1 1 1 1 1 1 1 1

A B AB

For Fun: XOR

A B A⊕B 1 1 1 1 1 1

For Fun: XOR

A B A⊕B 1 1 1 1 1 1

Few Final Notes

• Gates can have more than 2 inputs

w Generally keep number small due to electrical engineering issues

• Circuits that create current computers

are constructed from these basic gates

Equivalent

• Truth tables
• Circuit
• Boolean algebra expression

Truth tables are great for evaluating when circuit

• r Boolean expression evaluate to true

Combinatorial Logic: Multiplexor

23

Really a selector: One of the inputs is selected by the control C = (A * ~S) + (B * S)

Combinational Logic:
 Multiplexor

n:1 MUX 2n inputs n control 1 output n control lines select which of 2n inputs goes to output

n possible input lines requires ceiling(log2n) control lines. Equivalently, n control lines with 2n input lines.

1-bit MUX

AS + BS

Combinational Logic:
 De-Multiplexor

n:1 DEMUX 2n outputs n control 1 input n control lines select which of 2n outputs input goes to

1 to 2 De-multiplexor

Combinational Logic:
 Decoder

n control lines select which of 2n outputs set to 1 2n outputs n control

1 to 8 De-multiplexor

Combinational Logic:
 Encoder

One of 2n inputs set to 1. Output encodes which input set to 1. 2n inputs n bit output

4 to 2 Encoder

8 to 3 Encoder

33

Combinational Logic

• Comparator

w Given 2 inputs, sets output to 1 if inputs match

Combinational Logic

• Half-Adder

w No carry in

Combinational Logic

• Half-Adder

w No carry in

A B Sum Carry Out 1 1 1 1 1 1 1

A⊕B AB

1-bit Full Adder

• Three inputs:

w A w B w Cin

• Two outputs:

w Sum = (A⊕B) ⊕ Cin w Cout = AB + (A⊕B) Cin

Ripple Carry Adder

• Construct n-bit

adder with n 1-bit adders

• Delay is problem
• Faster alternative:

w Carry-lookahead adder