ECE 3060 VLSI and Advanced Digital Design Lecture 6 Gate Delay and Logical Effort ECE 3060 Lecture 6–1
First Model of Gate Delay • This model will be refined shortly ECE 3060 Lecture 6–2
Equivalent R • The average resistance of a MOSFET is someplace between the linear region, and saturation ECE 3060 Lecture 6–3
MOS Capacitor ECE 3060 Lecture 6–4
Capacitance Equations • Capacitors store charge • Q = CV charge is proportional to the voltage on a node • The equation can be put in a more useful form C Δ V dQ CdV ⇒ ⇒ Δ t - - - - - - - - - - - - - - - - - - - - - - i = i = = dt dt i • i = dQ/dt => i = C*(dV/dt) => (C*dV)/i = t • Thus, to change the node’s voltage (e.g., from 0 to 1), the transistor or gate driving that node must charge (up in our example) the capacitance associated with that node. The larger the capacitance, the large the required charge, and the longer it will take to switch the node. • Since of a transistor is approximately ⁄ i V R trans ECE 3060 Lecture 6–5
C Δ V C Δ V Δ t - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - = = = R trans C i ⎛ V ⎞ - - - - - - - - - - - - ⎝ ⎠ R trans ECE 3060 Lecture 6–6
Calculating R and C • pFET vs. nFET • Mobility ( µ ) of electrons twice mobility of holes • pFET resistance is twice nFET resistance • Series and Parallel Configurations • Series resistances add • Parallel: worst case is one transistor on • Transistor Sizing • Resistance Inversely Proportional to W / L • Gate Capacitance Proportional to W x L ECE 3060 Lecture 6–7
Symmetric Rise/fall? β n β p • Make , but then gate capacitance increased = 2 1 2 1 - - - - - - - - - - - - 1 1 1 1 1 1 1 1 - - - - - - - - - - - - 1 1 1 1 ECE 3060 Lecture 6–8
Tau Metric • We can normalize delay to technology independent τ units: for example may be defined by = RC • R is the resistance of a minimum size nFET • C is the gate capacitance of a minimum size inverter with equal rise and fall time: a minimum size nFET plus a double sized pFET ECE 3060 Lecture 6–9
Delay Example 2 • What is the delay for different values of A and B? • AB=01: 2 τ due to pFET mobility • AB=11: 2 τ due to series resistance • AB=10: 1 τ due to pFET mobility and W/L=2 ECE 3060 Lecture 6–10
Driving Large Loads • Suppose we wish to drive a large load, say equivalent to 100 inverters. What is the delay? C g C L δ • If the delay driving one inverter is , then the delay 100 δ driving is . C L W • Suppose we scale up the inverter, so the of each - - - - - L FET in the inverter increased by a factor of 100? δ • The delay driving the load goes down to , but the 100 δ delay driving the inverter itself goes up to . ECE 3060 Lecture 6–11
Minimizing Delay • Let’s consider driving the load with a chain of inverters W • Each inverter has ratios times the previous stage. - - - - - a L a τ • Each intermediate stage has delay . If this is true for C L C L 1 a n the last stage, we have or = - - - - - - - n = - - - - - - - - ln - - - - - - - C g ln a C g ⎛ ⎞ a C L Δ na τ - τ ⎜ ⎟ • Then total delay = = ln - - - - - - - - - - - - - - C G ln a ⎝ ⎠ ECE 3060 Lecture 6–12
Minimizing Delay (cont) d Δ Δ • To find the value of which minimizes , solve a = 0 d a ≈ ≈ which is minimized for a e 3 ≤ ≤ • In practice , and is often used. 2 a 10 a = 4 • Example: Using , design a circuit to drive 81 a = 3 inverters. ECE 3060 Lecture 6–13
C L 1 What to do when is not integral: - - - - - - - - n n = ln - - - - - - - ln a C g ECE 3060 Lecture 6–14
Fanin and Fanout • Fanin is the number of inputs to a complex gate • High fanin may imply long chains of FETs which will affect rise/fall times • Best results: chain lengths between two and five • Fanout is the number of gates driven by a gate • Output rise/fall times are proportional to output capacitance Fanin Fanout • For the next week, we will investigate the effect of fanin and fanout on gate delay in great detail. ECE 3060 Lecture 6–15
Goals of Method of Logical Effort • Learn how to design a combinational logic network with minimum delay • Learn how to take load into account • Example: a decoder output may drive hundreds of inverter equivalent loads • How many levels of logic are correct? • Which gates to use? • So many choices, so little time • Basic idea: • logical effort will describe the gate’s contribution to delay • electrical effort (fanout) will describe the capacitive load • Read Chapter 1 of Sutherland, Sproul and Harris ECE 3060 Lecture 6–16
Refining Calculation of Delay τ • As before, we will measure delay in units of , so = RC d τ that . d abs = τ • As before, we will use and , so that R = R inv C = C inv is the delay of a minimum size inverter (with equal rise and fall times) driving a minimum size inverter. τ ≈ • Note: in a 0.25 micron process 20ps • For now we will assume symmetric rise/fall times are required for all of our gates • Observe that so far we have not accounted for output capacitance of the logic gate itself in our delay calcu- lations. That is we have assumed that the delay of a gate with zero fanout is zero. This is about to change. ECE 3060 Lecture 6–17
Logical Effort of Inverter • Consider the effect of a particular choice of logic gate on (worst case) delay. • The logical effort of an inverter is defined to be 1. g ECE 3060 Lecture 6–18
Logical Effort of NAND • If we size transistors just like the inverter, the delay in the pull-down network will be twice that of pull-up (a) 2 (R) 2 (R) 2 (R) 2 (R) 1 (R) 2 (0.5R) 1 (R) 2 (0.5R) (a) (b) • If we resize the pulldown nFETs, we can drop the fall τ time back to , but we have increased the input capac- itance by one (to 4) (b) ECE 3060 Lecture 6–19
Logical Effort of NAND • If we scale (b) back so that 3/2 (4/3R) the input capacitance is the same as the inverter, the 3/2 (4/3R) delay rises by a factor ⁄ (c) . g = 4 3 3/2 (2/3R) • LE DEFINITION 1: So logical effort is the current delivery 3/2 (2/3R) ( ) ability of a gate with the R out (c) same as an inverter com- C in pared to the inverter . • LE DEFINITION 2: Alternatively, logical effort is the τ ratio of the input capacitance of a gate with delay (i.e., ) to the input capacitance of the inverter R out = R ECE 3060 Lecture 6–20
Electrical Effort and Delay • Electrical effort is defined to be the contribution of ⁄ fanout to delay . h = C load C in • So we have separated delay into three components: g • logical effort h • electrical effort p • parasitic delay • Now we can write d = gh + p = f + p • is called the stage effort f = gh • Parasitic delay is due primarily to the drain capaci- tance of the FETs connected to the output. ECE 3060 Lecture 6–21
Delay Plot ECE 3060 Lecture 6–22
Example: Three input NAND • What is ? g • Suppose we are driving 10 loads. What is ? f ECE 3060 Lecture 6–23
Table of LE ECE 3060 Lecture 6–24
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