Logical equivalence
Equivalence proof Multiplexers
January 22, 2020 Patrice Belleville / Geoffrey Tien 1
Logical equivalence Equivalence proof Multiplexers January 22, - - PowerPoint PPT Presentation
Logical equivalence Equivalence proof Multiplexers January 22, 2020 Patrice Belleville / Geoffrey Tien 1 Announcements Pre-class quiz #4, due Sunday, Jan.26, 19:00 Epp 4e/5e: Chapter 2.3 Pre-class quiz #5, due Sunday, Feb.02, 19:00
January 22, 2020 Patrice Belleville / Geoffrey Tien 1
– Epp 4e/5e: Chapter 2.3
– Epp 4e/5e: Chapter 3.1, 3.3
– Start the submission process early – there are several steps which may take a few minutes
January 22, 2020 Patrice Belleville / Geoffrey Tien 2
Name Rule Name Rule Identity laws 𝑞 ∧ 𝑈 ≡ 𝑞 𝑞 ∨ 𝐺 ≡ 𝑞 Universal bounds laws 𝑞 ∨ 𝑈 ≡ 𝑈 𝑞 ∧ 𝐺 ≡ 𝐺 Idempotent laws 𝑞 ∧ 𝑞 ≡ 𝑞 𝑞 ∨ 𝑞 ≡ 𝑞 Commutative laws 𝑞 ∨ 𝑟 ≡ 𝑟 ∨ 𝑞 𝑞 ∧ 𝑟 ≡ 𝑟 ∧ 𝑞 Associative laws 𝑞 ∨ 𝑟 ∨ 𝑠 ≡ 𝑞 ∨ 𝑟 ∨ 𝑠 𝑞 ∧ 𝑟 ∧ 𝑠 ≡ 𝑞 ∧ 𝑟 ∧ 𝑠 Distributive laws 𝑞 ∧ 𝑟 ∨ 𝑠 ≡ 𝑞 ∧ 𝑟 ∨ 𝑞 ∧ 𝑠 𝑞 ∨ 𝑟 ∧ 𝑠 ≡ 𝑞 ∨ 𝑟 ∧ 𝑞 ∨ 𝑠 Absorption laws 𝑞 ∨ 𝑞 ∧ 𝑟 ≡ 𝑞 𝑞 ∧ 𝑞 ∨ 𝑟 ≡ 𝑞 Negation laws 𝑞 ∨ ~𝑞 ≡ 𝑈 𝑞 ∧ ~𝑞 ≡ 𝐺 Double- negative law ~ ~𝑞 ≡ 𝑞 DeMorgan's laws ~ 𝑞 ∨ 𝑟 ≡ ~𝑞 ∧ ~𝑟 ~ 𝑞 ∧ 𝑟 ≡ ~𝑞 ∨ ~𝑟 Definition of ⨁ 𝑞⨁𝑟 ≡ 𝑞 ∨ 𝑟 ∧ ~ 𝑞 ∧ 𝑟 Definition of → 𝑞 → 𝑟 ≡ ~𝑞 ∨ 𝑟 Contrapositive law 𝑞 → 𝑟 ≡ ~𝑟 → ~𝑞
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– State the theorem we want to prove – Indicate the beginning of the proof by "Proof:" – Start with one side and work towards the other
trying to complicate the simpler one
– Indicate the end of the proof by "QED" or
January 22, 2020 Patrice Belleville / Geoffrey Tien 4
January 22, 2020 Patrice Belleville / Geoffrey Tien 5
~𝑏 ∧ 𝑐 ∨ 𝑏 ≡ 𝑏 ∨ ~𝑏 ∧ 𝑐 commutative law ≡ 𝑏 ∨ ~𝑏 ∧ 𝑏 ∨ 𝑐 distributive law ≡ ≡ 𝑏 ∨ 𝑐 identity law
a) 𝑏 ∨ 𝑐 b) 𝐺 ∧ 𝑏 ∨ 𝑐 c) 𝑏 ∧ 𝑏 ∨ 𝑐 d) Something else e) Not enough information to tell
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– Analogy: An HDMI switchbox for your TV
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Truth table
a b sel m F F F F F F T F F T F F F T T T T F F T T F T F T T F T T T T T 𝑛 = ~𝑡𝑓𝑚 ∧ 𝑏 ∨ 𝑡𝑓𝑚 ∧ 𝑐 ?
January 22, 2020 Patrice Belleville / Geoffrey Tien 9
Implementation
– If we change the input of a gate at time 𝑢 = 0 – the output of the gate will only reflect the change some time later – This time gap is called the gate delay
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a) 10 ns b) 20 ns c) 30 ns d) 40 ns e) It may never happen
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T F T T T T F
– assume the gate delay is 10ns
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F F T T T T F
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F T T T F T F
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F T T T F F T The output became F
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F T T T F T T The output became T again
– the information from 𝑡𝑓𝑚 travels on two different paths to the output – these paths contain different numbers of gates – the shorter path may affect the output until the information on the longer path catches up
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a) changing 𝑏 or 𝑐 only b) changing 𝑡𝑓𝑚, when exactly one of 𝑏, 𝑐 is F c) changing 𝑡𝑓𝑚, when both 𝑏, 𝑐 are F d) both (a) and (b) e) None of (a), (b), or (c)
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– ~𝑞 ∧ ~𝑟 ∨ 𝑞 ∧ 𝑟 ∧ 𝑠 ∨ ~𝑞 ∧ 𝑟 , to three literals – 𝑞 ∨ 𝑟 ∧ 𝑠 ∨ ~ 𝑞 ∨ 𝑠 , to two literals
– 𝑏 ∧ ~𝑐 ∨ ~𝑏 ∧ 𝑐 ≡ 𝑏 ∨ 𝑐 ∧ ~ 𝑏 ∧ 𝑐
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