Organisatorisches Verification Technology gy Prof. Dr.-Ing. Hans - PowerPoint PPT Presentation

1 Organisatorisches Verification Technology gy Prof. Dr.-Ing. Hans Eveking C Computer Systems Group t S t G Darmstadt University of Technology eveking@rs.tu-darmstadt.de

Computer Systems Group 2 Organisatorisches Verification Technology gy Prof. Dr.-Ing. H. Eveking "H "How to design digital hardware without bugs, t d i di it l h d ith t b and know it"

Computer Systems Group 3 Organisatorisches Verification Technology gy Prof. Dr.-Ing. H. Eveking  Prerequisites:  Basic knowledge in Boolean algebra + digital circuits  Basic knowledge in Boolean algebra + digital circuits (will repeat some basics next week)  Keywords:  Digital Systems  EDA (Electronic Design Automation)  Design Methodology  References:  Rapidly evolving area, no standard text R idl l i d d  No book covers all aspects, some aspects are not covered by any book covered by any book  References will be given chapterwise

Computer Systems Group 4 Verification Technology gy Prof. Dr.-Ing. H. Eveking  A few words about me ...  PhD in EE / habilitation in CS  PhD in EE / habilitation in CS  ´91-´95 professor ("Design Methodologies") in CS- Dept. of J.W.Goethe-University, Frankfurt p y,  Since ´95 professor ("Computer Systems") in EE&IT Dept. of Darmstadt Univ. of Technology

Computer Systems Group 5 Organisatorisches Verification Technology gy Prof. Dr.-Ing. H. Eveking  Lectures:  Wednesday 11.40-12.25 y S3 06/052  Thursday 11.40-13.10 S3 06/053  Exercises:  Wednesday 12.30-13.15 S3 06/052  Start: to be announced  Printed collection of slides will be distributed or are available in Room S3 06/329 (secretary)  also available on the web  Written exams in August-October 2011/April 2012  Simple questions, but 50% correct answers are required

Computer Systems Group 6 Verification Technology gy Prof. Dr.-Ing. H. Eveking   More verification ... More verification ... 15.7. 17.10. last last week Winter Summer term term term 10.-14.10. We are Lab (0+3) here here "Computer Systems Lab" Verification with industrial Guest-lecture on (Siemens/Infineon/OneSpin industrial verification: S l ti Solutions) tools ) t l Dr. Claudia Blank (Intel)

Computer Systems Group 7 0. Introduction: The Verification Problem f Verification Technology Content 0.1 What is correctness? 0 2 Protpotyping Synthesis Extraction Simulation 0.2 Protpotyping, Synthesis, Extraction, Simulation, Emulation 0.3 The Simulation Crisis 0.3 The Simulation Crisis 0.4 Formal Verification

8 0.1 What is correctness? 0.1 What is correctness?   Example Logic-Verification: show that two circuits Example Logic-Verification: show that two circuits implement the same Boolean function g a =1 1 b a & g g a a & & b & & b

9 0.1 What is correctness?  Correctness is relative to a specification — We can not say that the network of NAND-gates We can not say that the network of NAND-gates is correct by itself  A specification defines the meaning of correctness A specification defines the meaning of correctness — In the example, we have as a specification that the network of NAND-gates implements the XOR function g = a  b  In the following, we consider only "design correctness" (we do not discuss problems involved in the physical (we do not discuss problems involved in the physical realization of a design)   Verification establishes the correctness of a design Verification establishes the correctness of a design  In the hardware domain, "testing" means to , g detect defects due to the manufacturing process

10 0.1 What is correctness?  Correctness is a logical concept   In this lecture we consider correctness only at the In this lecture, we consider correctness only at the logic level  Consider only digital circuits  Consider only digital circuits  No treatment of analog circuits

11 0.1 What is correctness? Correctness  a  a   a a 1 1 Laws of Logic Logic Logical Mind Organisation      B Logic     IT- E d s d A  t System y A Laws of physics Physical Physical N t Nature Components Analysis

12 0.1 What is correctness? — Example: old mobile phone Analog part Digital Audio- RF- Signal- Interface Interface Interface Interface Processor P Display Display Micro- SIM card Controller ... Digital part

13 0.1 What is correctness?  The relevance of logical design correctness will be illustrated by means of two examples: y p  Pentium-Bug  Ariane 501 Ariane 501

14 0.1 What is correctness?  The effect of the Pentium bug at Intel $ $ 480.000.000 loss 1 0 9 0,9 0,8 0 7 0,7 0,6 0,5 0,5 0,4 0,3 0,3 0,2 0,1 0,1 0 1Q92 3Q92 1Q93 3Q93 1Q94 3Q94 1Q95 3Q95

15 0.1 What is correctness?  The "Pentium-Bug":  FP division algorithm of 1st generation of the Pentium  FP division algorithm of 1st generation of the Pentium processor had a bug  The problem was difficult to detect (theoreticians working with very large prime numbers discovered the bug)  Problem was not detected before many Pentium I were  P bl t d t t d b f P ti I sold ...  Intel was forced to take back the erroneous chips  Intel was forced to take back the erroneous chips  Hardware with errors is not accepted by the community (in contrast to software ...) y ( )  Pure "logical" design error (not a physical one)  Physical exchange of Pentium-Chips was a loss of Physical exchange of Pentium Chips was a loss of $ 480.000.000 for Intel  No patches for hardware ...

16 0.1 What is correctness?  History: Intel´s design roadmap in June 1992: 1980 1985 1990 1995 # Trans. 286 130.000 386 500.000 486 1.200.000 586 586 3.000.000 686 7.000.000 786 20.000.000

17 0.1 What is correctness?  The situation of the hardware designer:  The number of transistors per chip quadruples every 3  The number of transistors per chip quadruples every 3 years  At the same time, the time-to-market has to be reduced At the same time, the time to market has to be reduced  "Quality" software has ~ 1 undetected error per 1k LOC (lines of code) — A design of an ASIC in VHDL ( a standard hardware description language) has easily 100k LOC LOC  A redesign costs ~ 250 k€ (mask costs)  Th  The OS has to run on the first manufactured processor OS h t th fi t f t d chip!  How to get "zero-defect" VLSI ?  How to get zero-defect VLSI ?

18 0.1 What is correctness?  First launch of Ariane 501:  An overflow-situation in th the navigation computer was i ti t not handled correctly  The overflow resulted in a  The overflow resulted in a diagnosis message  The diagnosis message was The diagnosis message was wrongly interpreted as position information by the central computer computer  The central computer tried to correct the "wrong" position correct the wrong position by a sudden modification of the steering by > 20°  Cost: $ 500.000.000  "Purely logical" error

19 0.1 What is correctness?  Much more examples of design errors which were partially detected by formal verification techniques: y q  Motorola Fire-Chip Airbag-Controller: was able to fire the airbag in certain situations when the car was started  AMD K6 Processor: bug similar to Pentium  ...

20 0.1 What is correctness?  Example problems during the design of Pentium 4 (source: Bentley/Gray Intel Corp.): ( y y p )  "RTL Coding (18.1%)—These were things like typos, cut and paste errors, incorrect assertions (instrumentation) in the SRTL code, or the designer misunderstood what he/she was supposed to the designer misunderstood what he/she was supposed to implement.  Microarchitecture (25.1%)—This covered several categories: problems in the microarchitecture definition architects not problems in the microarchitecture definition, architects not communicating their expectations clearly to designers, and incorrect documentation of algorithms, protocols, etc.  L  Logic/Microcode Changes (18.4%)—These were bugs that i /Mi d Ch (18 4%) Th b th t occurred because: the design was changed, usually to fix bugs or timing problems, or state was not properly cleared or initialized at reset or these reset, or these were bugs related to clock gating. ere b gs related to clock gating  Architecture (2.8%)—Certain features were not defined until late in the project. This led to shoehorning them into working functionality."

21 0.1 What is correctness?  Two main sources of catastrophic failures:  Complexity of algorithms  Complexity of algorithms  Unforeseen interaction of parts

22 0.1 What is correctness? T Testability t bilit Correctness Low Cost Low Cost Design Quality Maintainability Maintainability Low Power Low Power Consumption D Dependability d bilit Security

23 0.1 What is correctness?  Correctness is essential  To avoid costly design iterations and recalls  To avoid costly design iterations and recalls  To ensure functionality in safety-critical applications