Introduction to Digital VLSI Design - - PowerPoint PPT Presentation

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Introduction to Digital VLSI Design - - PowerPoint PPT Presentation

Apr 03, 2024 334 likes •543 views

Introduction to Digital VLSI Design VLSI Extraction Lecturer: Gil Rahav Semester B , EE Dept. BGU. Freescale Semiconductors Israel Introduction to Digital VLSI Slide 1

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SLIDE 1

Introduction to Digital VLSI Slide 1

Introduction to Digital VLSI Design

  • ונכתלאובמ

VLSI יתרפס

Extraction Lecturer: Gil Rahav Semester B’ , EE Dept. BGU. Freescale Semiconductors Israel

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Introduction to Digital VLSI Slide 2

Extraction

  • Extraction is a process of creating

electrical representation (R&C) for layout interconnect

  • Extraction could be done in two ways:
  • 1. transistor level extraction
  • 2. cell level extraction

Resistance & Capacitance

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Introduction to Digital VLSI Slide 3

Delay calculation

Total delay = device delay + interconnect delay + slew rate

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Introduction to Digital VLSI Slide 4

Basic concepts

Capacitance

  • Area (overlap)
  • Fringe (edge)
  • Nearbody

(coupling)

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Introduction to Digital VLSI Slide 5

Parasitic Extraction

What is parasitic capacitance?

  • Electrical side effect depends on the shape of

the signal and its neighborhood.

  • Parasitic capacitance occurs both between

geometries on a single layer and between geometries on different layers.

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Introduction to Digital VLSI Slide 6

What is parasitic resistance?

  • Electrical side effect depend on the shape of

the signal and resistivity of the interconnect layer

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Introduction to Digital VLSI Slide 7

Grounding coupling capacitors

RC representation:

  • 1. C (lumped C)
  • 2. RC (distributed RC)
  • 3. RCC (distributed RC + coupling)

20 pF 20 pF 20 pF

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Introduction to Digital VLSI Slide 8

Layout formats

  • GDSII (stream)

raw geometrical shapes

  • LEF / DEF

geometric shapes + netlist

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Introduction to Digital VLSI Slide 9

GDSII format

  • Raw geometric shapes (polygons, paths) at

diffrenet layers

  • Texts (net names, pin names) at different layers
  • Cell instances

Available:

  • Always

Connectivity:

  • Requires connectivity analysis and LVS
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Introduction to Digital VLSI Slide 10

LEF (abstract)

  • Cell boundary
  • Cell pins with names and locations
  • Obstructions (used routing area)
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Introduction to Digital VLSI Slide 11

DEF

  • Represents one level of layout
  • Netlist, pins locations, cells placement,

routing annotated per net

  • Connectivity
  • All the information embedded inside the

LEF/DEF; no need for special processing Available from automatic P&R tools

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Introduction to Digital VLSI Slide 12

RC Formats

  • DSPF (= SPF) – most often used
  • SPEF
  • SPICE
  • SBPF

(for PrimeTime only)

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Introduction to Digital VLSI Slide 13

DSPF

  • resistance and line capacitance of each

segment in a net in a SPICE format Non SPICE statements:

  • *|NET NetName NetCap
  • *|I (InstancePinName InstanceName

PinName PinType PinCap X Y)

  • *|P (PinName PinType PinCap X Y)
  • *|S (SubNodeName X Y)
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Introduction to Digital VLSI Slide 14

*|NET cpm_ips_rdata[2] 0.129244PF *|P (cpm_ips_rdata[2] O 0 834.39 -0.27)

*|I (sba_env:cpm_ips_rdata[2] sba_env cpm_ips_rdata[2] B 0 317.67 90)

*|I (sbs_env/sbs_top:sbs_ips_rdata[2] *+ sbs_env/sbs_top sbs_ips_rdata[2] B 0 156.51 90) *|S (cpm_ips_rdata[2]:9) Cg1540 sba_env:cpm_ips_rdata[2] 0 1.16035e-14 Cg1541 cpm_ips_rdata[2] 0 5.46695e-14 Cg1542 cpm_ips_rdata[2]:9 0 1.1831e-14 Cg1543 sbs_env/sbs_top:sbs_ips_rdata[2] 0 5.114e-14 R1189 cpm_ips_rdata[2]:9 sbs_env/sbs_top:sbs_ips_rdata[2] 30.2 R1190 sba_env:cpm_ips_rdata[2] cpm_ips_rdata[2]:9 11.34 R1191 cpm_ips_rdata[2] cpm_ips_rdata[2]:9 25.8727

cpm_ips_rdata[2] sba_env:cpm_ips_rdata[2] sbs_env/sbs_top:sbs_ips_rdata[2]

Net nodes

Port node

Instance pin

Subnode

Capacitors Resistors Net name and total capacitance

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Introduction to Digital VLSI Slide 15

Extraction tools

  • xCalibre (GDSII)
  • Calibre2Star (GDSII)
  • StarXT (LEF / DEF)
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Introduction to Digital VLSI Slide 16

Target tools

  • Timing Analysis tools (Cell and Trasistor

Level)

  • Noise
  • Power grid
  • Circuit Verification Tools
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Introduction to Digital VLSI Slide 17

The Flows – Cell Level

  • Transistor level extraction on GDSII
  • LVS required
  • Usually extract capacitance only
  • Used for characterization, or in transistor

level analysis tool with cell level block extraction

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Introduction to Digital VLSI Slide 18

The Flows – Block Level

Transistor level Transistor level

Transistor level Cell level

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Introduction to Digital VLSI Slide 19

Chip level

  • extraction on LEF/DEF down to block

boundaries

  • no LVS required
  • extract RC
  • extraction tool - StarXt
  • analysis tool - PrimeTime
  • backannotation - no need
  • reduction - done on-the-fly
  • need to define context to model inside

blocks routing if obstructions do not exist