[PPT] - Logic Synthesis Page 1 Introduction to Digital VLSI Logic PowerPoint Presentation

SLIDE 1

Logic Synthesis

Page 1

Introduction to Digital VLSI

Logic Synthesis

SLIDE 2

Logic Synthesis

Page 2

Introduction to Digital VLSI

Course Outline

Design Compiler Overview
Some Words about Physical Compiler
Coding Styles
Partitioning
Design Compiler Commands
Additional Commands for Physical Compiler
Timing Analysis
Interaction with Layout Tools
Speed/Area Optimization
Logic Structure in High Level Code
Physical Compiler Overview

SLIDE 3

Logic Synthesis

Page 3

Introduction to Digital VLSI

Design Compiler Overview

Design Compiler

r mapped Gate Level

Cell Libraries Constraints Mapped Netlist HDL Code (RTL) (xxx.lib -> xxx.db) (timing and function) (timing, area ...)

SLIDE 4

Logic Synthesis

Page 4

Introduction to Digital VLSI

Physical Compiler Overview

Physical Compiler

r mapped Gate Level

Cell Libraries Constraints Placed Netlist HDL Code (RTL) Physical Libraries (cells and technology) (xxx.lib -> xxx.db) (xxx.plib -> xxx.pdb) (timing and function) Floorplan (timing & physical)

SLIDE 5

Logic Synthesis

Page 5

Introduction to Digital VLSI

synthesis = mapping + optimization

Speed Area

Large Small Fast Slow

Design Compiler is constraint-driven
Designer explores area vs. speed trade-offs simply by varying

constraints

SLIDE 6

Logic Synthesis

Page 6

Introduction to Digital VLSI

Few Synopsys rules of Thumb

“There is no ‘golden’ script for synthesis”
“The random setting of optimization switches and constraints to meet

your speed goals is NOT a credible methodology”

“Physics dictates what will fit between two clock edges”

SLIDE 7

Logic Synthesis

Page 7

Introduction to Digital VLSI

Analyze and Elaborate RTL code Apply Constraints Synthesize Constraints Met? End Identify Problem Re-code RTL Floorplan Create Custom Wireload

General Synopsys Synthesis Flow

No Yes

Synthesis tricks

SLIDE 8

Logic Synthesis

Page 8

Introduction to Digital VLSI

Analyze and Elaborate RTL code Apply Constraints compile_physical Constraints Met? End Identify Problem Re-code RTL “Floorplan”

General Synopsys Physical Synthesis Flow (mpc)

No Yes

including sime floorplan requirements

Create Floorplan

Synthesis tricks

r physopt

SLIDE 9

Logic Synthesis

Page 9

Introduction to Digital VLSI

Analyze and Elaborate RTL code Apply Constraints compile_physical Constraints Met? End Identify Problem Re-code RTL Update floorplan

General Synopsys Physical Synthesis Flow (flooplan based)

No Yes

including sime floorplan requirements Synthesis tricks

r physopt

(can be based

n mpc run)

Resize up/down, relocate pins etc. mpc run results

SLIDE 10

Logic Synthesis

Page 10

Introduction to Digital VLSI

Integrate Blocks Design End Top-Level Compile

Integration with Structures and other Blocks

Rule Problems?

Integration may cause transition problems (violations)
Top-level compile to fix any problem
Best way is to model the structures

Yes No

SLIDE 11

Logic Synthesis

Page 11

Introduction to Digital VLSI

Coding Style

Inferring Sequential Devices
Three-State Inference
Combinational Logic
case vs. if synthesis
Finite State Machines TBD? (Exists)?

SLIDE 12

Logic Synthesis

Page 12

Introduction to Digital VLSI

Inferring Sequential Devices

Synopsys can infer a broad range of FF’s and latches:
An inference report indicates type, width, and presence of: Bus, Async

Reset, Async Set, Sync Reset, Sync Set and Sync Toggle. Example: Inference Report for D Flipflop with Async Reset:

For more details refer to Synopsys on-line documentation.

Latch Latch w/ Async Latch w/Dual Async Latch w/ Sync DFF DFF w/ Async DFF w/Dual Async DFF w/ Sync Muxed DFF JKFF MS latch + + + + + + + + + + + Register Name Type Width Bus AR AS SR SS ST Q1_reg Flip-Flop 1

Y

N N N N

SLIDE 13

Logic Synthesis

Page 13

Introduction to Digital VLSI

D-Flip-Flops

module dffs (clk, in1, in2, cond, rst_b, out1, out2); input clk, in1, in2, cond, rst_b;

utput out1, out2;

reg out1, out2; always @(posedge clk) begin

ut1 <= in1;

end always @(posedge clk or negedge rst_b) begin if (!rst_b)

ut2 <= 1’b0;

else

ut2 <= in2;

end endmodule Always use non-blocking assignments for flip-flops. module dffs ( clk, in1, in2, cond, rst_b, out1, out2); input clk, in1, in2, cond, rst_b;

utput out1, out2;

dffrpc out2_reg ( .C(clk), .D(in2), .RB(rst_b), .Q(out2) ); dffpc out1_reg ( .C(clk), .D(in1), .Q(out1) ); endmodule

SLIDE 14

Logic Synthesis

Page 14

Introduction to Digital VLSI

Transparent Latches

module latches ( clk, in1, in2, rst_b, out1, out2); input clk, in1, in2, rst_b;

utput out1, out2;

reg out1, out2; always @(in1 or clk) begin if (clk)

ut1 <= in1;

end always @(in2 or rst_b or clk) begin if (!rst_b)

ut2 <= 1’b0;

else if (clk)

ut2 <= in2;

end endmodule Use non-blocking assignments for latches as well

SLIDE 15

Logic Synthesis

Page 15

Introduction to Digital VLSI

Transparent latches (cont.) - result of synthesis

Inferred memory devices in process in routine latches line 7 in file kuku =============================================================================== | Register Name | Type | Width | Bus | MB | AR | AS | SR | SS | ST | =============================================================================== | out1_reg | Latch | 1 | - | - | N | N | - | - | - | =============================================================================== Inferred memory devices in process in routine latches line 12 in file kuku =============================================================================== | Register Name | Type | Width | Bus | MB | AR | AS | SR | SS | ST | =============================================================================== | out2_reg | Latch | 1 | - | - | Y | N | - | - | - | ===============================================================================

SLIDE 16

Logic Synthesis

Page 16

Introduction to Digital VLSI

Transparent latches (cont.) - result of synthesis

module latches ( clk, in1, in2, rst_b, out1, out2 ); input clk, in1, in2, rst_b;

utput out1, out2;

itlrpc out2_reg ( .C(clk), .D(in2), .RB(rst_b), .Q(out2) ); itlpc out1_reg ( .C(clk), .D(in1), .Q(out1) ); endmodule

Note that the instance names of the latches are derived from the HDL

reg names.

SLIDE 17

Logic Synthesis

Page 17

Introduction to Digital VLSI

Gated Clocks

DC doesn’t understand that condition of the gated clock should have

setup time with regard to the clock. As a result there is a possibility for false select.

There is a danger of hold time violation when using gated clocks.

Checking hold time violations requires best case libraries.

Refrain from using gated clocks unless you put them into the clock

generator block.

From below you will see that the gated clocks problem exists for

multiple-clock flip-flops and for transparent latches.

Exception

New power compiler and clock tree synthesis flows enable manual

instatiation of gatded clcoks as well as automatic tool inference. User gated clocks in RTL source should be INTENTIONAL and include a latch and and AND function (glithless design). They should be used ONLY where Power Compiler has no ability to detect the shared clocking condition (e.g: stop/idle for global power saving).

SLIDE 18

Logic Synthesis

Page 18

Introduction to Digital VLSI

module gated_clock (clk1, clk2, in1, in2, cond, rst_b, out1, out2, out3); input clk1, clk2, in1, in2, cond, rst_b;

utput out1, out2, out3;

reg out1, out2, out3; wire clk; /* conditional flip-flop - no problem */ always @(posedge clk1 or negedge rst_b) begin if (!rst_b)

ut1 <= 1’b0;

else if (cond)

ut1 <= in1;

end /* conditional latch - refrain from using it */ always @(clk1 or rst_b or in1 or cond) begin if (!rst_b)

ut2 <= 1’b0;

else if (cond & clk1)

ut2 <= in1;

end /* multiple clocks flip-flop - refrain from using it */ assign clk = clk1 || clk2; always @(posedge clk or negedge rst_b) begin if (!rst_b)

ut3 <= 1’b0;

else

ut3 <= in2;

end endmodule

SLIDE 19

Logic Synthesis

Page 19

Introduction to Digital VLSI

Gated Clocks (cont.) - result of synthesis

module gated_clock ( clk1, clk2, in1, in2, cond, rst_b, out1, out2, out3 ); input clk1, clk2, in1, in2, cond, rst_b;

utput out1, out2, out3;

wire clk, n56, n164; mux21b z52 ( .A(out1), .B(in2), .S0(cond), .OUT(n164) ); dffrpb out1_reg ( .C(clk1), .D(n164), .RB(rst_b), .Q(out1) ); iand2b z51 ( .INPUT1(clk1), .INPUT2(cond), .OUTPUT1(n56) ); itlrpc out2_reg ( .C(n56), .D(in1), .RB(rst_b), .Q(out2) ); ior2b z50 ( .INPUT1(clk1), .INPUT2(clk2), .OUTPUT1(clk) ); dffrpc out3_reg ( .C(clk), .D(in2), .RB(rst_b), .Q(out3) ); endmodule

Note that gated clocks exist only on out2_reg and out3_reg.

SLIDE 20

Logic Synthesis

Page 20

Introduction to Digital VLSI

Gated Clocks (cont.) - how to prevent them

Don’t use multiple clocked flip-flops
Conditional latches could be implemented in the following way:

C D Q

TL

in1

ut1

clk && cond C D Q

TL

in1

ut1

C Q D

TL

clk_b clk 2->1 MUX cond

ut1_d
According to evaluation done in

Design2 the timing and area of the alternative implementation is only slightly worse than of the original

ne.
Explicit (“manual”) clock gating is

also possible if multiple latches shared one condition (power saving issue)

SLIDE 21

Logic Synthesis

Page 21

Introduction to Digital VLSI

// in the “clock generator”

utput clk_gated;

reg cond_latched; always @(clk or cond) if (~clk) cond_latched <= cond; assign clk_gated = (cond_latched | scan_enable) & clk; . . . // In the module input clk_gated; reg out; always @(posedge clk_gated or negedge rst_b) begin if (!rst_b)

ut <= 1’b0;

else

ut <= in;

end . . .

Gated Clocks (cont.) - explicit gated clocks

c_b d q

TL

clk cond scan_enable clk_gated

SLIDE 22

Logic Synthesis

Page 22

Introduction to Digital VLSI

Three-State Inference

A three-state driver is inferred when the value z is assigned to a

module ff_3state (data1, data2, clk, three_state, out1, out2); input data1, data2, clk, three_state;

utput out1;
utput out2;

reg out1; reg out2_data; always @ (posedge clk) begin if (three_state)

ut1 = 1’bz;

else

ut1 = data1;

end always @ (posedge clk)

ut2_data = data2;

assign out2 = three_state ? 1’bz : out2_data; endmodule

Do not use tristate buffers internal to a block.
DO not define bidirectinal ports for a synthesized block.

SLIDE 23

Logic Synthesis

Page 23

Introduction to Digital VLSI

module ff_3state ( data1, data2, clk, three_state, out1, out2 ); input data1, data2, clk, three_state;

utput out1, out2;

wire n98, n99, n100, n101; trinvc out2_tri ( .INPUT1(n98), .INPUT2(n99), .OUTPUT1(out2) ); iinve U21 ( .INPUT1(three_state), .OUTPUT1(n99) ); trinvc out1_tri ( .INPUT1(n100), .INPUT2(n101), .OUTPUT1(out1) ); dffpb out1_reg ( .C(clk), .D(data1), .QB(n100) ); dffpb out1_tri_enable_reg ( .C(clk), .D(three_state), .QB(n101) ); dffpb out2_data_reg ( .C(clk), .D(data2), .QB(n98) ); endmodule Inferred THREE-STATE control devices in process in routine ff_3state line 11 in file kuku. ============================================================================ | Three-state Device Name | Type | MB | ============================================================================ | out1_tri | Three-state Buffer | N | | out1_tri_enable_reg | Flip-flop (width 1) | N | ============================================================================

SLIDE 24

Logic Synthesis

Page 24

Introduction to Digital VLSI

Combinational Logic

Use combinational logic for:

Intermediate variables for clarity
Complex logic that becomes unwieldy in the FF always loop
Functions that are used more than once with different parameters
Resource Sharing

SLIDE 25

Logic Synthesis

Page 25

Introduction to Digital VLSI

wire yy = (A & C | (B != ‘GO)) ? D : (D & !A); wire start_count = start & (count < 17); reg y; always @(posedge clk) if (start_count) y <= yy; reg y; always @(posedge clk) if (start & (count < 17)) begin if (A & C | (B != ‘GO)) y <= D; else y <= D & !A; end reg yy; // not a real register always @(A or B or C or D) begin if (A & C | (B != ‘GO)) yy = D; else yy = D & !A; end reg y; always @(posedge clk) if (start & (count < 17)) y <= yy;

SLIDE 26

Logic Synthesis

Page 26

Introduction to Digital VLSI

DesignWare Resources

HDL Compiler understands some operators and automatically generates the logic to implement them:

+/- will use inc, dec, incdec, add, sub, addsub as appropriate
> >= < <= will generate a comparator

reg [7:0] a, b; reg [7:0] y; always @(posedge clk) if (a > b) y <= a + b;

comparator adder

SLIDE 27

Logic Synthesis

Page 27

Introduction to Digital VLSI

Case Synthesis

case statements infer "tall and skinny" muxes.

always @(SEL or A or B or C or D) begin case (SEL) 2’b00 : OUTC = A; 2’b01 : OUTC = B; 2’b10 : OUTC = C; default : OUTC = D; endcase end OUTC A B C D SEL 2 00 01 10 11 Note: Actual gates synthesized might not be a 4->1 MUX

SLIDE 28

Logic Synthesis

Page 28

Introduction to Digital VLSI

Case Synthesis (cont.)

Statistics for case statements in always block at line 8 in file kuku =============================================== | Line | full/ parallel | =============================================== | 11 | auto/auto | =============================================== Current design is now {"try1"}

SLIDE 29

Logic Synthesis

Page 29

Introduction to Digital VLSI

Case Synthesis (cont.) - WARNINGS!!!

If you do not specify all possible branches of the case statement HDL

Compiler will synthesize a latch.

If HDL Compiler can’t statically determine that branches are parallel, it

synthesizes hardware that includes a priority encoder.

SLIDE 30

Logic Synthesis

Page 30

Introduction to Digital VLSI

Case Synthesis - “full case”

A case statement is called full case if all possible branches

are specified.

Synopsys will synthesize a latch if you don’t specify all

possible branches of a case statement. Use // synopsys full_case directive immediately after the case expression if

always @(sel or a or b or c) begin case (sel) 2'b00 : outc <= a; 2'b01 : outc <= b; 2'b10 : outc <= c; endcase end A case statement that is Parallel but not Full And what is wrong here ?

SLIDE 31

Logic Synthesis

Page 31

Introduction to Digital VLSI

Case Synthesis - “full case” (cont.)

Synopsys statistics WITHOUT // synopsys full_case directive Statistics for case statements in always block at line 8 in file kuku =============================================== | Line | full/ parallel | =============================================== | 11 | no/auto | =============================================== Inferred memory devices in process in routine try2 line 8 in file kuku =============================================================================== | Register Name | Type | Width | Bus | MB | AR | AS | SR | SS | ST | =============================================================================== | outc_reg | Latch | 1 | - | - | N | N | - | - | - | =============================================================================== Current design is now try2

SLIDE 32

Logic Synthesis

Page 32

Introduction to Digital VLSI

Case Synthesis - “full case” (cont.)

always @(sel or a or b or c) begin case (sel) // synopsys full_case 2'b00 : outc = a; 2'b01 : outc = b; 2'b10 : outc = c; endcase end Synopsys statistics WITH // synopsys full_case directive Warning: You are using the full_case directive with a case statement in which not all cases are covered. (HDL-370) Statistics for case statements in always block at line 8 in file kuku =============================================== | Line | full/ parallel | =============================================== | 11 | user/auto | =============================================== Current design is now try2

Note: This is not a recomended style !

Blocking assignment

Prefer full description of the case.

SLIDE 33

Logic Synthesis

Page 33

Introduction to Digital VLSI

Case Synthesis - “parallel case”

A case statement is called parallel case if HDL Compiler can

determine that no cases overlap.

Synopsys will synthesize a priority encoder unless // synopsys

parallel_case directive is used.

always @(w or x) begin case (1'b1) w : b = 0; x : b = 1; endcase end A case statement that is Not Full or Parallel

SLIDE 34

Logic Synthesis

Page 34

Introduction to Digital VLSI

Case Synthesis - “parallel case” (cont.)

Synopsys statistics WITHOUT // synopsys parallel_case full_case directive Statistics for case statements in always block at line 7 in file kuku =============================================== | Line | full/ parallel | =============================================== | 10 | no/no | =============================================== Inferred memory devices in process in routine try3 line 7 in file kuku =============================================================================== | Register Name | Type | Width | Bus | MB | AR | AS | SR | SS | ST | =============================================================================== | b_reg | Latch | 1 | - | - | N | N | - | - | - | ===============================================================================

SLIDE 35

Logic Synthesis

Page 35

Introduction to Digital VLSI

Case Synthesis - “parallel case” (cont.)

Synopsys statistics WITH // synopsys parallel_case full_case directive Warning: You are using the full_case directive with a case statement in which not all cases are covered. (HDL-370) Warning: You are using the parallel_case directive with a case statement in which some case-items may overlap. (HDL-371) Statistics for case statements in always block at line 7 in file kuku =============================================== | Line | full/ parallel | =============================================== | 10 | user/user | =============================================== Current design is now try3

SLIDE 36

Logic Synthesis

Page 36

Introduction to Digital VLSI

if-then-else Synthesis

if-then-else statements infer priority-encoded "cascading" MUXs.

always @(SEL or A or B or C or D) begin if (SEL == 2’b00) OUTC = A; else if (SEL == 2’b01) OUTC = B; else if (SEL == 2’b10) OUTC = C; else OUTC = D; end D C 1 SEL == 2’b10 SEL 1 B 1 SEL == 2’b01 SEL == 2’b00 A OUTC Note: Actual gates synthesized might not match those shown above.

SLIDE 37

Logic Synthesis

Page 37

Introduction to Digital VLSI

case vs if statements

Note that only case statement may be implemented without priority

always @(. . .) begin if (. .) . . . ; else if (. .) . . . ; else if (. .) . . . ; else . . . ; end top priority always @(. . .) begin if (. .) . . . ; if (. .) . . . ; if (. .) . . . ; end always @(. . .) begin case (. .) A: . . . ; B: . . . ; C: . . . ; endcase end top priority top priority

SLIDE 38

Logic Synthesis

Page 38

Introduction to Digital VLSI

Safe Coding Rules

Sensitivity Lists

Use complete sensitivity lists for combinational always statements. Otherwise, pre-synthesis (high-level) simulation might not match post-synthesis (gate-level) simulation results. Elaboration will detect incomplete sensitivity lists and generate a warning.

A

always @(A) begin C = A || B; end

B C A B C

High-Level Simulation Synthesized Netlist

A B C

Gate-Level Simulation

SLIDE 39

Logic Synthesis

Page 39

Introduction to Digital VLSI

Safe Coding Rules (cont.)

case and if Statements (part 1)

Completely specify all clauses for every case and if statement.
Completely specify all outputs for every clause of each case or if

statement.

Failure to do so will cause extra latches or flip-flops to be synthesized.
In combinational always blocks - use blocking assignments

always @(D) begin case (D) 2’b00: Z <= 1’b1; 2’b01: Z <= 1’b0; 2’b10: Z <= 1’b1; S <= 1’b1; endcase end Missing Clause S Output What’s wrong with this code? non-blocking

SLIDE 40

Logic Synthesis

Page 40

Introduction to Digital VLSI

Safe Coding Rules (cont.)

case and if Statements (part 2)

Whenever possible, use a case statement with default (rather

than an if statement).

always @(SEL or INNER) case (SEL) 2’b00: Z = 2’b00; 2’b01: case (INNER) 2’b00: Z = 2’b11; 2’b01: Z = 2’b01; default: Z = 2’b00; endcase 2’b10: Z = 2’b11; default: Z = 2’b10; endcase case within a case

SLIDE 41

Logic Synthesis

Page 41

Introduction to Digital VLSI

Implication Example

Good style takes advantage of if-else priority to synthesize correct

Bad Style

case (STATE) IDLE: if (LATE == 1’b1) ADDR_BUS = ADDR_MAIN; else ADDR_BUS = ADDR_CNTL; INTERRUPT: if (LATE == 1’b1) ADDR_BUS = ADDR_MAIN; else ADDR_BUS = ADDR_INT; endcase if (LATE == 1’b1) ADDR_BUS = ADDR_MAIN; else case (STATE) IDLE: ADDR_BUS = ADDR_CNTL; INTERRUPT: ADDR_BUS = ADDR_INT; endcase

Good Style

COMBO LATE ADDR_MAIN ADDR_BUS COMBO LATE ADDR_MAIN ADDR_BUS

SLIDE 42

Logic Synthesis

Page 42

Introduction to Digital VLSI

Partitioning What is Partitioning? vs. SOG !

Partitioning is dividing a design into smaller parts.
How do you decide on the partitioning of your design?
By functionality
By designer’s skill
For optimal synthesis result
All of the above
Partitioning is done within the HDL description and/or the Design

SLIDE 43

Logic Synthesis

Page 43

Introduction to Digital VLSI

Partitioning Within the HDL Description

module ADR_BLK (. . . DEC U1 (ADR, CLK, INST); OK U2 (ADR, CLK, AS, OK); endmodule;

CLK AS ADR INST OK DEC OK

Module statements create hierarchical design blocks.
Continuous assignments and always@ statements do not create

ADR_BLK

SLIDE 44

Logic Synthesis

Page 44

Introduction to Digital VLSI

Partitioning Within Design Compiler

A designer can re-partition a design after it has been entered into

Design Compiler.

group ungroup

SLIDE 45

Logic Synthesis

Page 45

Introduction to Digital VLSI

The group command

U1

Creates a new hierarchical block containing the specified cells.
The designer provides a “design name” and a “cell name” for

the new block.

U2 U3 U4 U5 U6 U7 U8 U9 U10 group -logic -design DECODE

cell DEC1

U10 DECODE DEC1 U5

SLIDE 46

Logic Synthesis

Page 46

Introduction to Digital VLSI

The ungroup command

Removes levels of hierarchy of the named instances. Very

important command.

simple_names option should be used to remove the extra

DEC/U2 DEC/U3 DEC/U4 DEC/U5 U6 U7 U8 U9 U10 ungroup {DEC1} U6 U7 U8 U9 U10 DECODE DEC1 DEC/U1

SLIDE 47

Logic Synthesis

Page 47

Introduction to Digital VLSI

Why Partition for Synthesis?

Required less resources. (Tool, Designers)
Less timing constraints to deal with.
Further placement optimization is allowed.

Why SOG (Sea Of Gates) for Synthesis?

Produce the best synthesis results.
Speed up optimization run times.
Simplify the synthesis process.

SLIDE 48

Logic Synthesis

Page 48

Introduction to Digital VLSI

Partitioning Rules for Synthesis

No hierarchy in combinational paths.
Register all outputs.
No glue logic between blocks.
Separate designs with different goals.
Maintain a reasonable block size.
Separate logic, pads, clocks and non-synthesizable

structures.

SLIDE 49

Logic Synthesis

Page 49

Introduction to Digital VLSI

No Hierarchy in Combinational Paths

Bad Example

REG COMB LOGIC A

The path between two REG’s is divided between three different blocks.

Optimization is limited because hierarchical boundaries prevent

sharing of common terms.

COMB LOGIC B COMB LOGIC C REG

SLIDE 50

Logic Synthesis

Page 50

Introduction to Digital VLSI

No Hierarchy in Combinational Paths (cont.)

Better Example

REG COMB LOGIC

Related combinational logic is grouped into one block;

thus. all related combinational logic is at the same level
f hierarchy.

REG A & B & C

SLIDE 51

Logic Synthesis

Page 51

Introduction to Digital VLSI

No Hierarchy in Combinational Paths (cont.)

Best Example

REG COMB LOGIC

Related combinational logic is grouped into the same block that contains the destination register for the combinational logic path.

REG A & B & C

SLIDE 52

Logic Synthesis

Page 52

Introduction to Digital VLSI

No Glue Logic Between Blocks

Bad Example

REG CLK COMBO LOGIC A A REG CLK C COMBO LOGIC C A C TOP

A NAND gate was added to the TOP level block description, to “bridge” the two instantiated lower-level blocks

SLIDE 53

Logic Synthesis

Page 53

Introduction to Digital VLSI

No Glue Logic Between Blocks (cont.)

Good Example

REG CLK COMBO LOGIC A A REG CLK C A C TOP

Merge glue logic into the related combinational logic description of the lower-level architectural statements.

The merged glue logic can now be optimized away.

GLUE + COMBO LOGIC C

SLIDE 54

Logic Synthesis

Page 54

Introduction to Digital VLSI

Separate Designs with Different Goals

Bad Example

REG CLK CRITICAL PATHS A REG CLK C TOP

REG A is in the critical path, but REG C is not.

Optimization is limited because the designer cannot isolate parts of a

block and optimize them solely for area or for speed.

NO CRITICAL LOGIC

SLIDE 55

Logic Synthesis

Page 55

Introduction to Digital VLSI

Separate Designs with Different Goals (cont.)

Good Example

REG CLK CRITICAL PATHS A REG CLK C

Use different modules to partition the design into

NO CRITICAL LOGIC

SLIDE 56

Logic Synthesis

Page 56

Introduction to Digital VLSI

Maintain a Reasonable Block Size

Bad Example

10 gates

If blocks are too small, the designer may be restricting optimization

with artificial boundaries.

If blocks are too big, compile run times are very long; quick iterations

40,000 gates 10,000 gates 30,000 gates