ECE/CS 250 Computer Architecture Summer 2019 Basics of Logic Design: Storage Elements and the Register File (Sequential Logic) Tyler Bletsch Duke University Slides are derived from work by Daniel J. Sorin (Duke), Alvy Lebeck (Duke), and Drew Hilton (Duke)
So far… • We can make logic to compute “math” • Add, subtract … and you can do mul/div in 350 • Assume for now that mul/div can be built • Bitwise: AND, OR, NOT,… • Shifts (left or right) • Selection (MUX) • …pretty much anything • But processors need state (hold value) • Registers • … 2
Storage • All the circuits we looked at so far are combinational circuits: the output is a Boolean function of the inputs. • We need circuits that can remember values (registers, memory) • The output of the circuit is a function of the input and a function of a stored value (state) • Circuits with storage are called sequential circuits • Key to storage: feedback loops from outputs to inputs 3
Ideal Storage – Where We’re Headed • Ultimately, we want something that can hold 1 bit and we want to control when it is re-written “flip flop” = bit to be written device that bit currently being held holds one bit to control bit (0 or 1) when we write • However, instead of just giving it to you as a magic black box, we’re going to first dig a bit into the box • I will not test you on the insides of the “flip flop” 4
Building up to the D Flip-Flop and beyond D Q D Q R R D Q E D Q Q D Q D D D DFF Q Q Q Q D D DFF DFF latch latch DFF E E !Q DFF !Q E Q E Q C E Q Q E Q S Q E Q D S D Q D Q D Q D DFF 32 bit reg latch E E Q Q E Q SR Latch D Latch D Flip-Flop Register 5 (too awkward) (bad timing) (okay but only one bit) ( nice! )
FF Step #1: NOR-based Set-Reset (SR) Latch 0 0 R R 0 1 1 Q Q 0 0 1 1 0 0 Q Q 0 S S R S Q 0 0 Q 0 1 1 1 0 0 1 1 - Don’t set both S & R to 1. Seriously, don’t do it. 6
Set-Reset Latch (Continued) 0 0 R R 0 1 1 Q Q 0 0 1 1 0 0 Q Q 1 S S Time 1 S 0 1 R 0 1 Q 0 7
Set-Reset Latch (Continued) 0 0 R R 0 1 1 Q Q 0 0 1 1 0 0 Q Q 1 S S Time 1 S 0 Set Signal Goes High 1 R 0 1 Q 0 Output Signal Goes High 8
Set-Reset Latch (Continued) 0 0 R R 0 1 1 Q Q 0 0 1 1 0 0 Q Q 1 S S Time 1 S 0 Set Signal Goes Low 1 R 0 1 Q 0 Output Signal Stays High 9
Set-Reset Latch (Continued) 0 0 R R 0 1 1 Q Q 0 0 1 1 0 0 Q Q 1 S S Time 1 S 0 Until Reset Signal 1 R Goes High 0 1 Q 0 Then Output Signal Goes Low 10
SR Latch • Downside: S and R at once = chaos • Downside: Bad interface • So let’s build on it to do better 11
Building up to the D Flip-Flop and beyond D Q D Q R R D Q E D Q Q D Q D D D DFF Q Q Q Q D D DFF DFF latch latch DFF E E !Q DFF !Q E Q E Q C E Q Q E Q S Q E Q D S D Q D Q D Q D DFF 32 bit reg latch E E Q Q E Q SR Latch D Latch D Flip-Flop Register 12 (too awkward) (bad timing) (okay but only one bit) ( nice! )
FF Step #2: Data Latch (“D Latch”) R Q Q S Starting with SR Latch 13
Data Latch (D Latch) R E nable Q Q D ata S Starting with SR Latch Change interface to Data + Enable (D + E) If E=0, then R=S=0. If E=1, then S=D and R=!D 14
Data Latch (D Latch) R E nable D E Q Q 0 1 0 1 1 1 - 0 Q Q D ata S Time 1 D 0 E goes high 1 E 0 D “latched” 1 Q Stays as output 0 15
Data Latch (D Latch) R E nable D E Q Q 0 1 0 1 1 1 - 0 Q Q D ata S Time Does not affect Output 1 D 0 E goes low 1 E 0 Output unchanged 1 Q By changes to D 0 16
Data Latch (D Latch) R E nable D E Q Q 0 1 0 1 1 1 - 0 Q Q D ata S Time 1 D 0 E goes high 1 E 0 D “latched” 1 Q Becomes new output 0 17
Data Latch (D Latch) R E nable D E Q Q 0 1 0 1 1 1 - 0 Q Q D ata S Time 1 D 0 Slight Delay 1 E 0 (Logic gates take time) 1 Q 0 18
Logic Takes Time • Logic takes time: • Gate delays: delay to switch each gate • Wire delays: delay for signal to travel down wire • Other factors (not going into them here) • Need to make sure that signals timing is right • Don’t want to have races or wacky conditions.. 19
Clocks • Processors have a clock: • Alternates 0 1 0 1 • Like the processor’s internal metronome • Latch logic latch in one clock cycle One clock cycle • 3.4 GHz processor = 3.4 Billion clock cycles/sec 20
FF Step #3: Using Level-Triggered D Latches • First thoughts: Level Triggered • Latch enabled when clock is high • Hold value when clock is low D Q D Q D Logic D 3 3 latch latch E Q E Q Clk 21
Strawman: Level Triggered • How we’d like this to work • Clock is low, all values stable Clk 100 001 010 111 D Q D Q D Logic D 3 3 latch latch E Q E Q 0 Clk 22
Strawman: Level Triggered • How we’d like this to work • Clock goes high, latches capture and xmit new val Clk 100 100 010 010 D Q D Q D Logic D 3 3 latch latch E Q E Q 0 Clk 23
Strawman: Level Triggered • How we’d like this to work • Signals work their way through logic w/ high clk Clk 100 100 010 010 D Q D Q D Logic D 3 3 latch latch E Q E Q 0 Clk 24
Strawman: Level Triggered • How we’d like this to work • Clock goes low before signals reach next latch Clk 100 100 010 010 D Q D Q D Logic D 3 3 latch latch E Q E Q 0 Clk 25
Strawman: Level Triggered • How we’d like this to work • Clock goes low before signals reach next latch Clk 000 100 111 010 D Q D Q D Logic D 3 3 latch latch E Q E Q 0 Clk 26
Strawman: Level Triggered • How we’d like this to work • Everything stable before clk goes high Clk 000 100 111 010 D Q D Q D Logic D 3 3 latch latch E Q E Q 0 Clk 27
Strawman: Level Triggered • How we’d like this to work • Clk goes high again, repeat Clk 000 000 111 111 D Q D Q D Logic D 3 3 latch latch E Q E Q 0 Clk 28
Strawman: Level Triggered • Problem: What if signal reaches latch too early? • I.e., while clk is still high Clk 101 000 111 111 D Q D Q D Logic D 3 3 latch latch E Q E Q 0 Clk 29
Strawman: Level Triggered • Problem: What if signal reaches latch too early? • Signal goes right through latch, into next stage.. Clk 101 101 111 111 D Q D Q D Logic D 3 3 latch latch E Q E Q 0 Clk 30
That would be bad… • Getting into a stage too early is bad • Something else is going on there corrupted • Also may be a loop with one latch • Consider incrementing counter (or PC) • Too fast: increment twice? Eeek … 001 +1 D Q D latch E Q 010 3 31
Building up to the D Flip-Flop and beyond D Q D Q R R D Q E D Q Q D Q D D D DFF Q Q Q Q D D DFF DFF latch latch DFF E E !Q DFF !Q E Q E Q C E Q Q E Q S Q E Q D S D Q D Q D Q D DFF 32 bit reg latch E E Q Q E Q SR Latch D Latch D Flip-Flop Register 32 (too awkward) (bad timing) (okay but only one bit) ( nice! )
FF Step #4: Edge Triggered • Instead of level triggered • Latch a new value at a clock level (high or low) • We use edge triggered • Latch a value at an clock edge (rising or falling) Falling Edges Rising Edges 33
Our Ultimate Goal: D Flip-Flop D Q D Q D Q D D latch latch Q E E Q C • Rising edge triggered D Flip-flop • Two D Latches w/ opposite clking of enables 34
D Flip-Flop D Q D Q D Q D D latch latch Q E E Q C • Rising edge triggered D Flip-flop • Two D Latches w/ opposite clking of enables • On Low Clk, first latch enabled (propagates value) • Second not enabled, maintains value 35
D Flip-Flop D Q D Q D Q D D latch latch Q E E Q C • Rising edge triggered D Flip-flop • Two D Latches w/ opposite clking of enables • On Low Clk, first latch enabled (propagates value) • Second not enabled, maintains value • On High Clk, second latch enabled • First latch not enabled, maintains value 36
D Flip-Flop D D Q D Q D Q D Q D D D D latch latch latch latch E E Q E E Q C C • No possibility of “races” anymore • Even if I put 2 DFFs back-to- back… • By the time signal gets through 2 nd latch of 1 st DFF 1 st latch of 2 nd DFF is disabled • Still must ensure signals reach DFF before clk rises • Important concern in logic design “ making timing ” 37
D Flip- flops (continued…) • Could also do falling edge triggered • Switch which latch has NOT on clk • D Flip-flop is ubiquitous • Typically people just say “latch” and mean DFF • Which edge: doesn’t matter • As long as consistent in entire design • We’ll use rising edge 38
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