Why Again Logic Synthesis Giovanni De Micheli Why again logic - - PowerPoint PPT Presentation

Why Again Logic Synthesis

Giovanni De Micheli

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Why again logic synthesis?

§ Strong intellectual value associated with logic synthesis and optimization

§ Problems are far from being solved

§ Current methods and tools grew out of control and random logic design for CMOS semicustom libraries

§ Still inefficient for computational engines with predominance

• f arithmetic units

§ Emerging nanotechnologies

§ New devices are game changers

(c) Giovanni De Micheli

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The emerging nano-technologies

§ Enhanced silicon CMOS is likely to remain the main manufacturing process in the medium term

§ The 10nm and 7nm technology nodes are on the way

§ What are the candidate technologies for the 5nm node and beyond?

§ Silicon Nanowires (SiNW) § Tunneling FETs (TFET) § Carbon Nanotubes (CNT) § 2D devices (flatronics)

§ What are the common denominators from a design standpoint?

(c) Giovanni De Micheli

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22 nm Tri-Gate transistors

(c) Giovanni De Micheli

[Courtesy: M. Bohr]

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FinFET

Three-sided gate

NanoWire FET

Gate All Around

From FinFET to Nanowire FET

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Electrostatic doping

CG S D CG S D p-FET n-FET

§ Electrically program the transistor to either p-type or n-type § Field-effect control of the Schottky barrier

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Silicon Nanowire Transistors

§ Gate all around transistors § Double gate to control polarity

(c) Giovanni De Micheli

[Courtesy: De Marchi, EPFL]

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Device Id/Vcg

Vcg Vpg Vds=2V

• Vpg = 0V

Vpg = 2V Vpg = 4V

• 2

3 4

• Vcg [V]

Log( Id [A] )

• [Courtesy: De Marchi, IEDM 12 EPFL]

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Logic level abstraction

§ Three terminal transistors are switches

§ A loaded transistor is an inverter

§ Controllable-polarity transistors compare two values

§ A loaded transistor is an exclusive or (EXOR)

§ The intrinsic higher computational expressiveness leads to more efficient data-path design § The larger number of terminals must be compensated by smart wiring

(c) Giovanni De Micheli

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Logic cell design

§ CMOS technology is efficient only for negative-unate functions § INV, NAND, NOR, AOI § Controllable-polarity logic is efficient for all functions § Best for XOR-dominated circuits (binate functions)

Gnd Vdd

INV XOR2

Only 4 transistors when compared to 8 transistors with a regular CMOS

Vdd A A Vdd Gnd Gnd B B Y

NAND2

Similar to regular CMOS

Negative Unate functions Binate functions

[Courtesy: H. Ben Jamaa, ’08] (c) Giovanni De Micheli

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Modular physical cell design

NAND2 ¡ XOR2 ¡ Two ¡transistor ¡pairs ¡ grouped ¡together ¡ Tile ¡

G2 g1 G1 G2 g2 G1 n1 n2 n3 n6 n5 n4 (c) Giovanni De Micheli

[Courtesy: Bobba, DAC 12]

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Modeling various emerging nanogates

(c) Giovanni De Micheli

A B CNFETs SiNWFETs Graphene FETs Reversible Logic 6T Nanorelays 4T Nanorelays

t" c2" (c1"c2"…"cn)""""t"

⊕

c1" cn" c2" c1" cn"

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Biconditional Binary Decision Diagrams

§ Native canonical data structure for logic design § Biconditional expansion:

f (v,w,.., z) = (v ⊕ w) f (w',w,.., z)+(v⊕w) f (w,w,.., z)

§ Each BBDD node:

§ Has two branching variables § Implements the biconditional expansion § Reduces to Shannon’s expansion for single-input functions

PV=v f(v,w,..,z) f(w’,w,..,z) f(w,w,..,z) SV=w PV=SV PV=SV

[Courtesy: Amaru’, JETCAS 14]

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BBDD: Examples

= = 1 = = = = = = 1 = =

a b c d e g a b c d

a) b)

b 1 f=ab+(a⊕b)(c⊕d) π=(a,b,c,d) f=a⊕b⊕c⊕d⊕e⊕g π=(a,b,c,d,e,g)

= = 1 = =

a b c 1

c)

b 1 f=ab+bc+ac π=(a,b,c)

= = 1 =

a b c 1

d)

b c π=(a,b,c)

= = = = = = =

f=(a⊕b)(b+c)

§ The BDD counterparts for these examples have about 50% more nodes!

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Efficient direct mapping of BBDD nodes

f(w,w,..,z) f(w’,w,..,z) f(v,w,..,z)

1

v f(v,w,..,z) f(w’,w,..,z) f(w,w,..,z) w = BBDD MUX-XNOR

=

v w f(w’,w,..,z) f(w,w,..,z) f(v,w,..,z) v w v w v w v w Transistor-level Implementation

[Courtesy: Amaru’, DATE 13]

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Compact BBDD representations

=

a0 b0 S0

= =

a0 b0 b0

1 = =

a1 b1 S1

= =

a1 b1

1

b1

1 = =

a2 b2 S2

= =

a2 b2 Cout b2

= 1 1

§ n-bit adder size: § 3n+1 nodes § BDD counterpart: § 5n+2 nodes

3-bit adder

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Compact BBDD representations

a

= = =

c b

1 1 1

b c b

= = = =

e d d c

1

c d c

= = =

e d

= = =

g f f e

=

e d

= = 1

d

= =

MAJ5(a,b,c,d,e) MAJ3(a,b,c) MAJ7(a,b,c,d,e,f,g)

§ n-bit majority size: § 0.25 (n2 + 7) nodes § BDD counterpart: §

⌈0.5n⌉(n−⌈0.5n⌉+1)+1 nodes

7-bit majority

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The BBDD optimization tool

§ Recursive formulation of Boolean operations § Unique table to store BBDD nodes § Performance-oriented memory management § Chain variable reordering

(c) Giovanni De Micheli

BBDD Package

BBDD

http://lsi.epfl.ch/BBDD

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Experimental results

(c) Giovanni De Micheli

§ We implemented a BBDD package in C language

§ Comparison with CUDD (BDD)

§ Both CUDD and BBDD first build the diagrams and then apply sifting

1.54e04 1.24e04

8.00E+03 1.00E+04 1.20E+04 1.40E+04 1.60E+04 CUDD BBDD Node count

• 19.5%

Also 1.63x speedup for arithmetic intensive circuits

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Case study: arithmetic restructuring

§ Use BBDD to restructure arithmetic circuits prior to synthesis § Front-end to a commercial synthesis tool § Real-life telecommunication design: Iterative Product Code Decoder

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Nanotechnology design

§ Iterative Product Code Decoder § Analysis after Physical Design:

§ 22 nm FINFET § 22-nm DG-SiNWFET

[Courtesy: Amaru’, IEEE Proceedings 15]

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Logic synthesis for design and assessment

(c) Giovanni De Micheli

Emerging technologies Comparison to CMOS New tools Technology evaluation

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§ Emerging nano-technologies with enhanced-functionality devices increase computational density § New design, synthesis and verification methods stem from new abstractions of logic devices § Current logic synthesis is based on specific heuristics: new models with stronger properties lead us to better methods and tools for both CMOS and emerging devices

Conclusions

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Thank you

(c) Giovanni De Micheli

Never stop exploring !!!