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VLSI VLSI
- Digital Signal Processing
Digital Signal Processing -
- Hsie-Chia Chang
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VLSI VLSI - Digital Signal Processing Digital Signal Processing - - - PowerPoint PPT Presentation
VLSI VLSI - Digital Signal Processing Digital Signal Processing - - - PowerPoint PPT Presentation
VLSI VLSI - Digital Signal Processing Digital Signal Processing - - - Hsie-Chia Chang E-mail : hcchang@mail.nctu.edu.tw Fall 2006 Course I nformation Course I nformation Mission This course will cover the most important
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Related Course Related Course
計算機概論 計算機程式設計 資料結構 邏輯設計 數位電路與系統 電子學、電路學 工程數學 計算機組織 VLSI設計導論 IC LAB(I)(II) 通訊原理 數位訊號處理 數位積體電路設計 類比積體電路設計 電腦輔助設計 VLSI訊號處 理架構設計 混合訊號積體電路設計測試 射頻積體電路設計 數位通訊 高等數位訊號處理 SOC設計概論
基礎課程 ( 大一、大二 ) 核 心 課 程 ( 大三、大四 ) 進階課程
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Course Content (1/ 3) Course Content (1/ 3)
High-level Architectural Transformation
– Iteration Bound
- Chap. 2
– Pipelining and Parallel Processing Chap. 3 – Retiming
- Chap. 4
– Unfolding
- Chap. 5
– Folding
- Chap. 6
– Systolic Architecture Design
- Chap. 7
High-level algorithm Transformation
– Fast Convolution
- Chap. 8
– Algorithm Strength Reduction in Filters and Transforms
- Chap. 9
– Pipelined and Parallel Recursive and Adaptive Filter
- Chap. 10
– Scaling and Roundoff Noise
- Chap. 11
– Digital Lattice Filter Structures
- Chap. 12
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Course Content (2/ 3) Course Content (2/ 3)
High-performance VLSI architecture & systems
– Bit-level Arithmetic Architectures
- Chap. 13
– Redundant Arithmetic
- Chap. 14
– Numerical Strength Reduction
- Chap. 15
– Synchronous, Wave, and Asynchronous Pipelines Chap. 16 – Low-Power Design
- Chap. 17
– Programmable Digital Signal Processors
- Chap. 18
Appendix
– Shortest Path Algorithms、Scheduling and Allocation Techniques – Euclidean GCD Algorithm、Orthonormality of Schur Polynomials – Fast Binary Adders and Multipliers、Scheduling in Bit-Serial Systems – Coefficient Quantization in FIR Filters
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Course Content (2/ 3) Course Content (2/ 3)
Lecture 01: Overview
- Chap. 1, 2
Lecture 02: Pipelining & Retiming
- Chap. 3, 4
Lecture 03: Unfolding Transformation
- Chap. 5
Lecture 04: Folding Transformation
- Chap. 6
Case Study I : 2D-ACS Unit for Viterbi Decoders Lecture 05: Systolic Arrays
- Chap. 7
Lecture 06: Algorithmic Strength Reduction
- Chap. 9
Case Study I I : FFT Processors Lecture 07: Bit-Serial Architectures
- Chap. 13 (I )
Lecture 08: Redundant Arithmetic
- Chap. 14
Lecture 09: Numerical Strength Reduction
- Chap. 15
Lecture 10: Distributed Arithmetic
- Chap. 13 (I I )
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Course Content (3/ 3) Course Content (3/ 3)
Grading
– Homework + Project report 40% – Midterm exam. 30% – Final exam. 30%
Final Project
– The project can be individual project or a group project – Project type can be either theory/algorithm development or implementation – Project report is required to be submitted before the end of this semester – Project presentation will take place in class
Teaching Assistant
– 郭羽庭 ED412, 5712121 ext.54225, ytkuo@twins.ee.nctu.edu.tw – ???
Course Website
– http://oasis2.ee.nctu.edu.tw/VLSI_DSP
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