IFIP/IEEE VLSI-SoC 18 th International Conference on Very Large - - PowerPoint PPT Presentation

ifip ieee vlsi soc 18 th international conference on very
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IFIP/IEEE VLSI-SoC 18 th International Conference on Very Large - - PowerPoint PPT Presentation

IFIP/IEEE VLSI-SoC 18 th International Conference on Very Large Scale Integration on Very Large Scale Integration VLSI-SoC 2010 (Madrid, Spain) September 27-29, 2010 Prof. David Atienza The City: Madrid Easily accessible EU & America


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SLIDE 1

IFIP/IEEE VLSI-SoC 18th International Conference

  • n Very Large Scale Integration
  • n Very Large Scale Integration

VLSI-SoC 2010 (Madrid, Spain)

September 27-29, 2010

  • Prof. David Atienza
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SLIDE 2

The City: Madrid

  • Easily accessible EU & America
  • >30 flights daily EU

j i i i

  • Easyjet, Virgin, RyanAir, …
  • >20 flights daily from Americas
  • Historical city

Puerta Puerta Alcala Alcala Plaza Mayor Plaza Mayor Prado Museum Prado Museum

y

  • Largest city in Spain: 602 KM2
  • Population: 5.84M
  • Romans & Muslims (9th)

y

  • Romans & Muslims (9th)
  • Cosmopolitan
  • 2006: 40% foreigners

Royal Palace Royal Palace Buen Retiro Park Debod’s Debod’s Temple Temple

  • Complete transportation
  • 10 metro lines, 150 buses
  • Large academic tradition

y Royal Palace Royal Palace p Debod s Debod s Temple Temple

Large academic tradition

  • 12 universities (6 public, 7 priv.)

Atocha Atocha Train Station Train Station Twin Kio (bended) Towers Twin Kio (bended) Towers

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SLIDE 3

Location – CS School/UCM

  • Created in 1991 (new building in 2003)
  • Students: ~3000 ; Teachers: ~200 (still growing)

Students: 3000 ; Teachers: 200 (still growing)

  • Facilities
  • Auditorium with capacity for 150 attendees
  • 3 Meeting rooms: capacity from 35 to 80 people
  • Cafeteria and registration desk
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SLIDE 4

Technical Programme (1/2)

  • Invited keynote speakers:
  • Invited keynote speakers:

– Prof. Subhasish Mitra, Stanford U. – Prof. Giovanni De Micheli, EPFL , – Dr. Sani Nassif, IBM – Prof. Nick Dutt, UC Irvine

  • Special industrial session

– Green computing and datacenters: IBM Zürich, Google, Yahoo, ST IBM Zürich, Google, Yahoo, ST – Bioengineering VLSI

  • Hotels prices for you to come!

Conference special theme:

Green computing

  • Hotels prices for you to come!
  • single: 65-100€/night

– (163 B$-250B$/night)

Green computing

  • double: 80-120€/night

– (200 B$-300B$/night)

. .

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SLIDE 5

Technical Programme (2/2)

Day 1 ‐ Monday, September 27th Day 2 ‐ Tuesday, September 28th Day 3 ‐ Wednesday, September 29th 8:30‐9:00 Registration and Opening 8:30‐9:00 9:00‐9:30 Keynote 1 (Auditorium) Keynote 2 (Auditorium) 9:00‐9:30 9:30‐10:00

  • Prof. Subhasish Mitra ‐ Stanford Univ.
  • Prof. Giovanni De Micheli (EPFL)

9:30‐10:00 10:00‐10:30 Coffee break Coffee break Keynote 3 (Auditorium) 10:00‐10:30 10:30‐11:00 Session 1 Session 2 Session 5 Session 6

  • Dr. Sani Nassif ‐ IBM

10:30‐11:00 11:00‐11:30 Coffee break 11:00‐11:30 11:30‐12:00 Session 9 Session 10 11:30‐12:00 12:00‐12:30 12:00‐12:30 12:30‐13:00 Lunch Lunch 12:30‐13:00 13:00‐13:30 Lunch 13:00‐13:30 13:30 14:00 Keynote 2 (Auditorium) Session 7 Session 8 13:30 14:00 13:30‐14:00 Keynote 2 (Auditorium) Session 7 Session 8 13:30‐14:00 14:00‐14:30

  • Prof. Nikil Dutt ‐ UC. Irvine

(Special Session 1) Session 11 Session 12 14:00‐14:30 14:30‐15:30 Poster Session 1 "Green Computing" ( Special Session 2) 14:00‐15:30 15:30‐16:00 and coffee break Coffee break Coffee break 15:30‐16:00 16:00‐18:00 Session 3 Session 4 PhD Forum Session 13 Session 14 16:00‐18:00 18:00‐20:00 Social event (tour in Madrid) 18:00‐20:00 21:00‐1:00 Gala dinner with flamenco show 21:00‐1:00

. .

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SLIDE 6

2 Social Events (visit to Madrid and 2 Social Events (visit to Madrid and dinner, flamenco and… dancing test)

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SLIDE 7

Final Call for Papers

  • Website already open:
  • Easychair system (free),

DUDE replication

  • f

papers

  • DUDE

replication

  • f

papers (CEDA)

  • Paper/PhD Submissions:

March 28, 2010 S i l S i P l

  • Special Session Proposal:

March 28, 2010

  • Notification of acceptance:

Notification of acceptance: June 16, 2010

  • Camera-ready:

July 11, 2010

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SLIDE 8

Organizing Committee (1/2)

  • General Chair
  • General Chair

David Atienza, EPFL, Switzerland

 Program Co-Chairs

Andrea Acquaviva Politecnico di Torino Italy Andrea Acquaviva, Politecnico di Torino, Italy Jose L. Ayala, Complutense U. (UCM), Madrid, Spain Rajesh Gupta, UCSD, CA, USA

 Panels/Special Sessions Co-Chairs  Panels/Special Sessions Co-Chairs

Ayse K. Coskun, Boston University, USA Luca Benini, Univ. of Bologna, Italy

 Publications Co-Chairs Publications Co Chairs

Ricardo Reis, UFRGS, Brazil Jose I. Hidalgo, Olcoz, UCM, Madrid, Spain

 Publicity Co-Chairs Publicity Co Chairs

Praveen Raghavan, IMEC, Belgium

 PhD Forum Co-Chairs

Matthew Guthaus, UCSC, USA Matthew Guthaus, UCSC, USA Andreas Burg, ETHZ, Switzerland

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SLIDE 9

Organizing Committee (2/2)

 Finance/Local arrangements Chair

Katzalin Olcoz, UCM, Spain d i i C ill h S i Fernando Rincon, Univ. Castilla La Mancha, Spain

  • Steering Committee VLSI-SoC

Manfred Glesner, TU Darmstadt, Germany Luis M. Silveira, INESC ID, Portugal Salvador Mir, TIMA, France Ricardo Reis, UFRGS, Brazil Michel Robert, U. Montpellier, France  Institutional Relations Co-Chairs

Francisco Tirado, UCM, Spain Román Hermida, UCM, Spain

  • Invited Members of IFIP WG10.5 & IFIP/EEE VLSI SoC
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SLIDE 10

Topics Technical Programme

 12 Topics, 2 Co-Chairs per topic:

 Analog, Digital, and Mixed-Signal IC Design  3 D Integration and Physical Design  3-D Integration and Physical Design  Deep Submicron Design and Modeling Issues, New Devices and MEMS  CAD and Tools Testability and Design for Test  CAD and Tools, Testability and Design for Test  Digital Signal Processing and Image Processing IC Design  Prototyping, Validation, Verification, Modeling and Simulation S t Chi D i  System-on-Chip Design  Embedded Systems Design and Real-Time Systems  New Architectures and Compilers, Reconfigurable Systems  Logic and High-Level Synthesis  New Applications (bio-systems, sensor networks, automotive, security, communications, etc.)  Low-Power Design

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SLIDE 11

Income and Financial support

  • Registration fees (break-even with 80 regs.)

– IEEE/IFIP students (7%/3%), 225 € / 480 € IEEE/IFIP students (7%/3%), 225 € / 480 € – IEEE/IFIP Members (45%/5%), 400 € / 600 € – NO IEEE/IFIP Students (27%/3%), 400 € / 550 € NO IEEE/IFIP M b (7%/3%) 550 € / 700 € – NO IEEE/IFIP Members (7%/3%), 550 € / 700 €

  • TOTAL EXPECTED (100 people):

~50,000 €

  • Sponsoring

– IFIP, WG 10.5 (50%) IEEE C il EDA (CEDA 25%) – IEEE Council on EDA (CEDA, 25%) – IEEE Circuits and Systems Society (CASS, 25%) – CS School and Complutense University p y – Spanish Research Agency (~5000 €)

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SLIDE 12

VLSI-SoC 2010 (www.vlsi-soc.com) See you next in October i M d id! in Madrid!