[PPT] - SoC SoC Design SoC SoC Design Design Design Lecture Lecture 1 PowerPoint Presentation

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SoC SoC Design Design SoC SoC Design Design

Lecture Lecture 1 1: Introduction : Introduction

Shaahin Hessabi Shaahin Hessabi Department of Computer Engineering Department of Computer Engineering Department of Computer Engineering Department of Computer Engineering Sharif University of Technology Sharif University of Technology

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System System-on

n-
Chip

Chip

System: a set of related parts that act as a whole to achieve

System: a set of related parts that act as a whole to achieve a given goal. a given goal.

A system is a set of interacting components, which has

A system is a set of interacting components, which has inputs and outputs, and exhibits specific behavior. inputs and outputs, and exhibits specific behavior.

Behavior: a function that translates inputs into outputs

System: an entity consisting of hardware and software

H d hi h d l ti l i H d hi h d l ti l i

Hardware: high speed, low power consumption, less price

Hardware: high speed, low power consumption, less price (probably) (probably)

Software: flexibility, ease of modification and upgrade

Software: flexibility, ease of modification and upgrade y, pg y, pg

Hardware system: a system whose physical components

Hardware system: a system whose physical components are electronic blocks are electronic blocks

Analog

Digital

Digital Mi d i l Mi d i l

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Mixed signal

SoC: Introduction

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Digital vs. Analog Systems Digital vs. Analog Systems

The critical advantage of digital systems is their ability to

The critical advantage of digital systems is their ability to deal with electrical signals that have been degraded. deal with electrical signals that have been degraded.

Due to the discrete nature of the outputs, a slight variation in an

Due to the discrete nature of the outputs, a slight variation in an input is still interpreted correctly. input is still interpreted correctly.

In

In analog analog circuits, a slight error at the input generates an circuits, a slight error at the input generates an t th t t t th t t error at the output. error at the output.

The simplest form of a digital system is binary.

The simplest form of a digital system is binary. A bi i l bi i l i i d l d d l d t ki l t di t t ki l t di t

A

A binary signal binary signal is is modeled modeled as taking on only two discrete as taking on only two discrete values ( values (0 0 or

r 1

1, LOW or HIGH, False or True). , LOW or HIGH, False or True).

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Advantages of Digital Systems Advantages of Digital Systems

1. 1.

High noise immunity High noise immunity

2

Adjustable precision Adjustable precision

2. 2.

Adjustable precision Adjustable precision

3. 3.

Less sensitivity to variations in components and Less sensitivity to variations in components and environmental parameters (especially temperature) environmental parameters (especially temperature) environmental parameters (especially temperature) environmental parameters (especially temperature)

4. 4.

Ease of design ( Ease of design ( automation) and fabrication, and automation) and fabrication, and therefore, low cost therefore, low cost therefore, low cost therefore, low cost

5. 5.

Better reliability Better reliability

6

Less need to calibration and maintenance Less need to calibration and maintenance

6. 6.

Less need to calibration and maintenance Less need to calibration and maintenance

7. 7.

Ease of diagnosis and repair Ease of diagnosis and repair

8

Easy to duplicate similar circuits Easy to duplicate similar circuits

8. 8.

Easy to duplicate similar circuits Easy to duplicate similar circuits

9. 9.

Easily controllable by computer Easily controllable by computer

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Disadvantages of Digital Systems Disadvantages of Digital Systems

1. 1.

Lower speed Lower speed N d l t di it l (A/D) d di it l t l (D/A) N d l t di it l (A/D) d di it l t l (D/A)

2. 2.

Need analog to digital (A/D) and digital to analog (D/A) Need analog to digital (A/D) and digital to analog (D/A) converters to communicate with real world; therefore, converters to communicate with real world; therefore, more expensive or less precise more expensive or less precise more expensive or less precise more expensive or less precise

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Contemporary Digital Design Contemporary Digital Design

Major changes in digital design in recent years:

Major changes in digital design in recent years:

More complex designs

More complex designs New methodologies and techniques required, New methodologies and techniques required, like like SoC SoC

Shorter time

Shorter time-

to

to-

market (TTM)

market (TTM)

Cheaper products

Cheaper products p p p p

Scale

Scale

Pervasive use of computer

Pervasive use of computer-

aided design tools over hand methods

aided design tools over hand methods M lti l l l f d i t ti M lti l l l f d i t ti

Multiple levels of design representation

Multiple levels of design representation

Time

Time

Emphasis on abstract design representations

Emphasis on abstract design representations p g p p g p

Programmable rather than fixed function components

Programmable rather than fixed function components

Automatic synthesis techniques

Automatic synthesis techniques

Importance of sound design methodologies

Importance of sound design methodologies

Importance of sound design methodologies

Importance of sound design methodologies

Cost

Cost

higher levels of integration

higher levels of integration

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use of simulation to debug designs

use of simulation to debug designs

SoC: Introduction

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Software Tools Software Tools

Digital design need not involve any software tools; however,

Software tools are nowadays an essential part of digital design

Software tools are nowadays an essential part of digital design.

HDLs (

HDLs (Hardware Description Languages Hardware Description Languages) and the corresponding simulation ) and the corresponding simulation and synthesis tools are widely used. and synthesis tools are widely used.

In a CAD (Computer

In a CAD (Computer-

Aided Design) environment, the tools improve

Aided Design) environment, the tools improve the productivity and help in correcting errors and predicting the productivity and help in correcting errors and predicting behavior behavior. .

Schematic entry;

HDLs compilers, simulators and synthesis tools;

Timing analysers;

Simulators

Test benches.

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Integrated Circuits (ICs) Integrated Circuits (ICs)

An IC is a collection of gates/blocks/... fabricated on a single silicon

An IC is a collection of gates/blocks/... fabricated on a single silicon chip chip chip. chip.

ICs are classified by their size:

SSI (small scale integration):

SSI (small scale integration): 1 1 to to 30 30 gates gates ( g ) ( g ) g

a small number of gates.

a small number of gates.

MSI (medium scale integration):

MSI (medium scale integration): 30 30 to to 300 300 gates gates decoder register counter decoder register counter

decoder, register, counter.

decoder, register, counter.

LSI (large scale integration):

LSI (large scale integration): 300 300 to to 300 300, ,000 000 gates gates

small memories, PLDs.

small memories, PLDs.

VLSI (very large scale integration): >

VLSI (very large scale integration): > 1 1, ,000 000, ,000 000 transistors transistors

microprocessors, memories.

microprocessors, memories.

The Core

The Core 2 2 Extreme QX Extreme QX9650 9650 Quad Core Processor (Intel Quad Core Processor (Intel 2008 2008 45 45

The Core

The Core 2 2 Extreme QX Extreme QX9650 9650 Quad Core Processor (Intel Quad Core Processor (Intel 2008 2008, , 45 45 nm technology) has nm technology) has 820 820 million transistors ( million transistors (420 420 M transistors per die) M transistors per die)

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Implementation Technologies Implementation Technologies

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Modern Systems Modern Systems

Basic elements:

Basic elements:

Microprocessors, buses and ASICs.

Microprocessors, buses and ASICs. p , p ,

Basic problems:

Basic problems:

HW/SW partitioning.

HW/SW partitioning. HW/SW HW/SW i l ti (i l di i ti d li ) i l ti (i l di i ti d li )

HW/SW co

HW/SW co-

simulation (including communication modeling).

simulation (including communication modeling).

Different design trade

Different design trade-

offs.
ffs.
Separate HW and SW design flows.

Separate HW and SW design flows. g

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What is an SoC? What is an SoC?

SoC Concept in the past simply implied higher levels of SoC Concept in the past simply implied higher levels of integration (Moore’s law): integration (Moore’s law): A i l hi l h h l l i hi A i l hi l h h l l i hi

A single chip replaces the whole multichip system

A single chip replaces the whole multichip system-

on
n-
board

board

Different chips on PCB (

Different chips on PCB (Printed Circuit Board Printed Circuit Board) are now ) are now Different chips on PCB ( Different chips on PCB (Printed Circuit Board Printed Circuit Board) are now ) are now building blocks ( building blocks (cores cores) of SoC chip ) of SoC chip

Advantages:

On On chip interconnects are man times faster than off chip interconnects are man times faster than off chip ires chip ires

On

On-chip interconnects are many times faster than off chip interconnects are many times faster than off-chip wires chip wires

Get a compact system with the same functionality

Reduces pin overhead

– – Saves much power

Saves much power

– – Reduces noise in the mixed

Reduces noise in the mixed-

signal/analog circuits

signal/analog circuits

Lower overall cost

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What is an SoC? (cont’d) What is an SoC? (cont’d) ( ) ( )

Today’s concept: gaining overall productivity gains through Today’s concept: gaining overall productivity gains through reusable design and integration of components reusable design and integration of components

Complex IC that

Complex IC that g g p g g p p integrates the major integrates the major functional elements of a functional elements of a complete end complete end-

product

product into a single chip using into a single chip using intellectual property (IP) intellectual property (IP) intellectual property (IP) intellectual property (IP) blocks. blocks.

IPs: pre

IPs: pre-

designed and

designed and p g pre pre-

verified

verified

Also called: virtual

Also called: virtual components components

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components components

SoC: Introduction

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Design Productivity Gap Design Productivity Gap g y p g y p

, , the IEEE, the IEEE, 06 06 edings of t edings of t June June 200 200 Procee Procee

SoC/IP approach improves the situation

Platform

Platform-

Based Design improves it further

Based Design improves it further

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Inside an Inside an SoC SoC

An

An SoC SoC usually contains: usually contains:

Reusable

Reusable IP IP

– Requires connecting computational units to communication medium

Requires connecting computational units to communication medium

Embedded processor, memory

Real

Real-world interface (wireless receiver/transmitter ) world interface (wireless receiver/transmitter )

Real

Real world interface (wireless receiver/transmitter, …) world interface (wireless receiver/transmitter, …)

Sensor

Mixed

Mixed-

signal blocks

signal blocks

Programmable hardware

RTOS and embedded software, device drivers

Has more than

Has more than 500 500 K gates K gates

Has more than

Has more than 500 500 K gates, K gates,

Uses .

Uses .25 25 μm μm technology or below technology or below

Is not an ASIC

Primary difference from ASIC: in SOC design, the goal is to

Primary difference from ASIC: in SOC design, the goal is to maximize reuse of existing blocks or “cores” maximize reuse of existing blocks or “cores”

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Why Why SoC SoC ? ? y

Increased functionality/performance in reduced footprint

Tighter design schedule

Bandwidth and performance

Simplified PCB design

Increased product mechanical robustness

Lower power consumption

Technology scaling

Lower system cost

…

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System System-in in-a-Package (SIP) Package (SIP)

SoC

SoC technology technology – – a great success, EXCEPT for radio a great success, EXCEPT for radio receiver/transmitters receiver/transmitters

System System in in a Package (SIP) Package (SIP)

receiver/transmitters receiver/transmitters

Can sustain mixed analog/digital hardware together on one chip,

Can sustain mixed analog/digital hardware together on one chip, provided that: provided that: A l h d i i th l A l h d i i th l f b d f b d

– – Analog hardware is in the low

Analog hardware is in the low-

frequency band

frequency band

– – Digital clocks & their harmonics are carefully chosen to avoid

Digital clocks & their harmonics are carefully chosen to avoid polluting key parts of the spectrum with noise polluting key parts of the spectrum with noise

Key result: Still unable to integrate radio frequency (RF)

Key result: Still unable to integrate radio frequency (RF) hardware into hardware into SoC SoC

– – Substrate coupling between digital and analog parts causes

Substrate coupling between digital and analog parts causes Substrate coupling between digital and analog parts causes Substrate coupling between digital and analog parts causes digital clock noise to destroy the signal digital clock noise to destroy the signal-

to

to-noise ratio of RF noise ratio of RF part part

– – RF tuners still require precision inductors but on

RF tuners still require precision inductors but on-chip chip RF tuners still require precision inductors, but on RF tuners still require precision inductors, but on chip chip inductors are expensive and inadequate inductors are expensive and inadequate

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System System-

in

in-

a

a-Package (SIP) Package (SIP) y g ( ) g ( )

Interim solution: Combine separate digital & analog chips

Interim solution: Combine separate digital & analog chips and passive components into a single package (SIP or and passive components into a single package (SIP or and passive components into a single package (SIP, or and passive components into a single package (SIP, or MCM= Multi MCM= Multi-

Chip Module)

Chip Module)

Common

Common 2 2-

D or

D or 3 3-

D substrate

D substrate

May contain SoC as one of the chips

Proceedings of the IEEE, Proceedings of the IEEE, June June 2006 2006 J

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SoC SoC Challenges Challenges

Increasing complexity

Time

Time-to to-market pressure market pressure

Time

Time to to market pressure market pressure

Verification bottleneck

Integration

Integration g g

Hardware

Hardware v.s v.s. software . software

Digital circuits

Digital circuits v.s v.s. . analog analog circuits circuits

Testing issues

Deep submicron effects

Ti i l bl Ti i l bl

Timing closure problem

Signal integrity problem

Reliability problem

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Time Time-

to

to-

Market Pressure

Market Pressure

Pressure from shorter product lifespan Pressure from shorter product lifespan An additional key factor in TTM, specific for SoC: An additional key factor in TTM, specific for SoC: System System integration = integration = integrating different silicon IPs on the same IC integrating different silicon IPs on the same IC

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g g g g g

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Time Time-

to

to-

Market Pressure (cont’d)

Market Pressure (cont’d)

Profit model showing the value of TTM:

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Verification Bottleneck Verification Bottleneck

Verification becomes the major bottleneck of the modern

Verification becomes the major bottleneck of the modern design flows design flows

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SoC SoC Challenges Challenges

Increasing complexity

Time

Time-to to-market pressure market pressure

Time

Time to to market pressure market pressure

Verification bottleneck

Integration

Integration g g

Hardware

Hardware v.s v.s. software . software

Digital circuits

Digital circuits v.s v.s. . analog analog circuits circuits

Testing issues

Deep submicron effects

Ti i l bl Ti i l bl

Timing closure problem

Signal integrity problem

Reliability problem

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HW/SW Integration HW/SW Integration

Integrating HW/SW at the final step may require high

Integrating HW/SW at the final step may require high cost. cost.

Early integration (HW/SW codesign)

Early integration (HW/SW codesign) Trend toward increasing design Trend toward increasing design complexity due to integration complexity due to integration complexity due to integration complexity due to integration

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Challenges for Mixed Signal Designs Challenges for Mixed Signal Designs

Design challenges

Chi Chi l l i l ti t k t h ti l l i l ti t k t h ti

Chip

Chip-

level simulation takes too much time

level simulation takes too much time

Design budgets are not distributed in a well

Design budgets are not distributed in a well-

defined manner

defined manner

Too much time is spent on low

Too much time is spent on low-level iterations level iterations

Too much time is spent on low

Too much time is spent on low level iterations level iterations

Design is not completely systematic

There is limited or no use of HDL

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SoC Testing Challenges SoC Testing Challenges

Distributed design and test

C id d t k th t t i t C id d t k th t t i t

Core provider does not know the target environment

System integrator is responsible for manufacturing testing

Test access

Bed

Bed-

of
f-nails (decomposition) system testing is not possible

nails (decomposition) system testing is not possible

Most of the cores are surrounded by many other cores

R lt i t ll bilit d R lt i t ll bilit d b bilit b bilit

– Results in very poor controllability and

Results in very poor controllability and observability

bservability

– Need electronic test hardware to access these blocks during testing

Need electronic test hardware to access these blocks during testing

– Bandwidth, I/O pin count limitations

Bandwidth, I/O pin count limitations

Test optimization

Minimizing test cost while satisfying constraints such as power,

Minimizing test cost while satisfying constraints such as power, resources coverage etc resources coverage etc resources, coverage, etc. resources, coverage, etc.

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SoC SoC Challenges Challenges

Increasing complexity

Time

Time-to to-market pressure market pressure

Time

Time to to market pressure market pressure

Verification bottleneck

Integration

Integration g g

Hardware

Hardware v.s v.s. software . software

Digital circuits

Digital circuits v.s v.s. . analog analog circuits circuits

Testing issues

Deep submicron effects

Ti i l bl Ti i l bl

Timing closure problem

Signal integrity problem

Reliability problem

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Timing Closure Problem Timing Closure Problem

Traditional silicon design flows: used statistical wire

Traditional silicon design flows: used statistical wire-

load

load models to estimate metal interconnects for pre models to estimate metal interconnects for pre-

layout timing

layout timing l i l i analysis analysis

load on a specific node: estimated by the sum of the input

load on a specific node: estimated by the sum of the input capacitances of the gates being driven capacitances of the gates being driven

statistical wire estimate based on the size of the block and the

statistical wire estimate based on the size of the block and the number of gates being driven number of gates being driven

Correct for

Correct for 250 250 nm and above, because the gate propagation nm and above, because the gate propagation delays and gate load capacitances dominate delays and gate load capacitances dominate

Wire delay starts to dominate total delay in DSM process

Lack of physical information about wire length

Only statistical wire delay model can be used at design phase

Inaccurate because they represent a statistical value based on the

Inaccurate because they represent a statistical value based on the block si e block si e block size block size

Incorrect estimations require long iterations to meeting timing

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Signal Integrity, Reliability Signal Integrity, Reliability

Feature size ↓→ sub

Feature size ↓→ sub-

wavelength lithography (impacts

wavelength lithography (impacts

f process variation), noise, cross
f process variation), noise, cross-
talk, SEU, reliability

talk, SEU, reliability

Frequency ↑, dimension ↑ →interconnect delay,

Frequency ↑, dimension ↑ →interconnect delay, l t ti fi ld ff t ti i l l t ti fi ld ff t ti i l electromagnetic field effects, timing closure electromagnetic field effects, timing closure

Supply voltage ↓→ signal integrity (noise, IR drop,

Supply voltage ↓→ signal integrity (noise, IR drop, etc) etc) etc) etc)

Wiring level ↑→ manufacturability

Wiring level ↑→ manufacturability Power consumption ↑ power & thermal issues Power consumption ↑ power & thermal issues

Power consumption ↑→ power & thermal issues

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General Architecture of General Architecture of Core Core-

Based SoC

Based SoC

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Design Flow Design Flow

Traditional Design Flow: Traditional Design Flow:

1

Front Front-end design end design

1. 1.

Front Front-end design end design

Begins with system definition in behavioral or algorithmic form

Begins with system definition in behavioral or algorithmic form and ends with floor planning and ends with floor planning

2. 2.

Back Back-

end design

end design

Begins with placement/routing through layout release (tape

Begins with placement/routing through layout release (tape-

out)
ut)

Engineers in either phase don’t know much about the

ther phase
ther phase

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Design Flow (cont’d) Design Flow (cont’d)

Vertical Integrated Design Environment: Vertical Integrated Design Environment: E i h f ll ibilit f bl k f t E i h f ll ibilit f bl k f t

Engineers have full responsibility for a block from system

Engineers have full responsibility for a block from system design specifications to physical design prior to chip design specifications to physical design prior to chip-

level integration

level integration level integration level integration

Necessary for functional verification of complex blocks with post

Necessary for functional verification of complex blocks with post-

layout timing

layout timing

Avoids last minute surprises related to block aspect ratio, timing,

Avoids last minute surprises related to block aspect ratio, timing, routing, or architectural and area/performance trade routing, or architectural and area/performance trade-

offs
ffs

Must be familiar with several CAD tools in a complex EDA

Must be familiar with several CAD tools in a complex EDA environment environment

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Task responsibilities of an engineer in a Task responsibilities of an engineer in a rti l d i n n ir nm nt rti l d i n n ir nm nt vertical design environment vertical design environment

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