[PPT] - SoC Design SoC Design g L Lecture Lecture 6: IP Cores 6 IP C : PowerPoint Presentation

SLIDE 1

SoC Design SoC Design g

L 6 IP C IP C Lecture Lecture 6: IP Cores : IP Cores

Shaahin Hessabi Shaahin Hessabi Department of Computer Engineering Department of Computer Engineering Sharif University of Technology Sharif University of Technology

SLIDE 2

IP Core IP Core

Intellectual Property (IP) core: predesigned and pre

Intellectual Property (IP) core: predesigned and pre-

verified modules used in ASIC/SOC designs.

verified modules used in ASIC/SOC designs. g

A Virtual Components (VC) with well

A Virtual Components (VC) with well-

defined functions, usage

defined functions, usage method, and tools to support its usage. method, and tools to support its usage.

Benefits:

Reduce time

Reduce time-

to

to-

market by

market by f d i f d i means of design reuse means of design reuse

Reduce the possibility of

Reduce the possibility of failure failure

Drawback:

Designing an IP block

Designing an IP block generally requires greater generally requires greater effort and higher cost effort and higher cost

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Resources versus Number of Uses Resources versus Number of Uses

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Design Reuse Design Reuse g

Design with reuse can have a significant impact:

IP blocks should have well

IP blocks should have well-defined interfaces defined interfaces

IP blocks should have well

IP blocks should have well defined interfaces. defined interfaces.

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SLIDE 4

What Is an IP Core? What Is an IP Core?

At least

At least 5 5K gates, K gates,

Pre

Pre-designed designed

Pre

Pre-designed, designed,

Pre

Pre-

verified,

verified,

Re

Re-usable usable

Re

Re-usable, usable,

H/W S/W Functional Blocks.

Examples:

Processor: ARM

Processor: ARM7 7, ARM , ARM9 9, and ARM , and ARM10 10, ARC, Leon. , ARC, Leon.

DSP cores: TI TMS

DSP cores: TI TMS320 320C C54 54X, Pine, Oak, MPEG X, Pine, Oak, MPEG-

2, MPEG

, MPEG-

4

4. . , , , , , , ,

Mixed signal: ADCs, DACs, Audio

Mixed signal: ADCs, DACs, Audio Codecs Codecs, PLLs, , PLLs, OpAmps OpAmps. .

Encryption:

Encryption: PKuP PKuP, DES. , DES.

I/Os: PCI, USB,

I/Os: PCI, USB, 1394 1394, , 1284 1284, E , E-

IDE, IrDA.

IDE, IrDA.

Miscellaneous: UARTs, DRAM Controller, Timers, Interrupt

Miscellaneous: UARTs, DRAM Controller, Timers, Interrupt Controller DMA Controller Controller DMA Controller

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Controller, DMA Controller. Controller, DMA Controller.

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SLIDE 5

Environment Environment

Core Providers:

What do I need to deliver a “product” while protecting technology

What do I need to deliver a product while protecting technology

What do I need to deliver a product while protecting technology and avoiding downstream liabilities? and avoiding downstream liabilities?

Core Users:

Core Users:

How do I effectively use external components?

How do I guarantee that the end product works?

F d S i F d S i

Foundry Services.

Foundry Services.

Standards Folks:

Standards Folks:

D fi i t f / t d d / th d t i i i D fi i t f / t d d / th d t i i i d t h t h

Define interfaces/standards/methods to maximize mix

Define interfaces/standards/methods to maximize mix-

and

and-match. match.

The

The Legals Legals: :

Clarify responsibilities and liabilities

Clarify responsibilities and liabilities.

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SLIDE 6

Advantages of Core Advantages of Core-

Based Design

Based Design

Allows to functionally verify each complex function block

Allows to functionally verify each complex function block with post with post-

layout timing as soon as RTL design and

layout timing as soon as RTL design and simulation are completed. simulation are completed.

Makes the back

Makes the back-

end physical data available at the front

end physical data available at the front-

end of the design cycle where it can influence algorithm

end of the design cycle where it can influence algorithm end of the design cycle, where it can influence algorithm end of the design cycle, where it can influence algorithm and/ or architecture trade and/ or architecture trade-

offs (Coupling physical and
ffs (Coupling physical and

system design). system design).

Bridging the gap between front end and back end

Bridging the gap between front end and back end virtually eliminates timing uncertainty virtually eliminates timing uncertainty

It i ibl t t It i ibl t t l t l t iti iti

It is possible to use post

It is possible to use post-layout layout parasitics parasitics. .

Results:

Results:

More time for block design (block

More time for block design (block- level timing convergence) but level timing convergence) but

More time for block design (block

More time for block design (block level timing convergence), but level timing convergence), but net savings net savings 25 25% to % to 30 30% on the overall timing convergence (chip % on the overall timing convergence (chip-

level) and gate

level) and gate-

level debugging.

level debugging.

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SLIDE 7

Marketplace Experiences Marketplace Experiences

Small IP:

Blocks requiring

Blocks requiring 1-2 staff years to design are priced at staff years to design are priced at 1/3 of the

f the

Blocks requiring

Blocks requiring 1 2 2 staff years to design are priced at staff years to design are priced at 1/3 3 of the

f the

development cost. development cost.

Buyers are skeptical about the value and often prefer to do these

Buyers are skeptical about the value and often prefer to do these in in house house in in-house. house.

Medium IP:

Blocks requiring

Blocks requiring 5-10 10 staff years are profitable for both seller and staff years are profitable for both seller and

Blocks requiring

Blocks requiring 5-10 10 staff years are profitable for both seller and staff years are profitable for both seller and buyer. buyer.

STAR IP:

Blocks requiring

Blocks requiring 100 100+ staff years to design (like ARM, MIPS ) + staff years to design (like ARM, MIPS ) have become bestsellers and come with lots of support. have become bestsellers and come with lots of support.

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SLIDE 8

Core Types Core Types-

Soft Cores

Soft Cores

Soft cores (“code”):

RTL (or higher level) description, to provide functional descriptions of

RTL (or higher level) description, to provide functional descriptions of IP IP IPs. IPs.

Maximum flexibility and

Maximum flexibility and reconfigurability reconfigurability, i.e., can be changed to suit an , i.e., can be changed to suit an application. application.

Must be synthesized, optimized, and verified by user before integration

Must be synthesized, optimized, and verified by user before integration into designs. into designs.

– quality of a soft IP depends on the effort needed in the IP

quality of a soft IP depends on the effort needed in the IP integration stage. integration stage.

Technology independent: may be re

Technology independent: may be re-

synthesized across processes.

synthesized across processes.

Significant IP protection risks.

Significant IP protection risks. g p g p

May

May include include macroblocks macroblocks or

r megacells

megacells, typically designed at the , typically designed at the physical level. physical level.

– Soft core provider supplies behavioral or functional models for the

Soft core provider supplies behavioral or functional models for the Soft core provider supplies behavioral or functional models for the Soft core provider supplies behavioral or functional models for the megacells megacells used in the core (for simulating the core at high levels). used in the core (for simulating the core at high levels).

– The core user has to implement the technology

The core user has to implement the technology-

dependent

dependent megacells megacells—a potentially challenging task. a potentially challenging task.

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g p y g g p y g g

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SLIDE 9

Core Types Core Types-

Firm Cores

Firm Cores yp yp

Firm cores (“

Firm cores (“code+structure code+structure”): ”):

role of firm IPs in ASIC design flow role of firm IPs in ASIC design flow

Targeted gate

Targeted gate-

level

level netlists netlists to to specific physical libraries after specific physical libraries after going through synthesis without going through synthesis without g g g y g g g y performing the physical layout. performing the physical layout.

– To be placed and routed.

To be placed and routed.

Str ct rall and topologicall Str ct rall and topologicall

Structurally and topologically

ptimized for performance and
ptimized for performance and

area through floor area through floor-

planning and

planning and placement. placement.

– using a range of process

using a range of process technologies technologies

Exist as synthesized code or as a

Exist as synthesized code or as a netlist netlist of generic library elements.

f generic library elements.

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Core Types Core Types-

Hard Cores

Hard Cores

Hard cores (“physical”):

Consist of hard layouts using particular physical design libraries.

Delivered in masked

Delivered in masked-

level designed blocks (GDSII format).

level designed blocks (GDSII format).

Ready for “drop in.”

Ready for “drop in.” I t ti f h d IP i it i l I t ti f h d IP i it i l

– – Integration of hard IP cores is quite simple.

Integration of hard IP cores is quite simple.

Include layout and timing (technology dependent).

Optimized implementation highest performance for their chosen

Optimized implementation, highest performance for their chosen

Optimized implementation, highest performance for their chosen physical library. physical library.

Minimum flexibility and portability in reconfiguration and

Minimum flexibility and portability in reconfiguration and i t ti lti l d i d t h l i i t ti lti l d i d t h l i integration across multiple designs and technologies. integration across multiple designs and technologies.

IP is easily protected.

Mostly processors and memory

Mostly processors and memory.

Functional test vectors or ATPG vectors available.

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Advantages/disadvantages of hard core Advantages/disadvantages of hard core

Ease of use

Developer already designed and tested core

– – Can use right away

Can use right away

– – Can expect to work correctly

Can expect to work correctly

Predictability Predictability

Predictability

Size, power, performance predicted accurately

Not easily mapped (retargeted) to different process

E.g., core available for vendor X’s

E.g., core available for vendor X’s 0 0. .25 25 micrometer CMOS micrometer CMOS process process Can’t use with vendor X’s Can’t use with vendor X’s 0 18 18 micrometer process micrometer process

– – Can t use with vendor X s

Can t use with vendor X s 0.18 18 micrometer process micrometer process

– – Can’t use with vendor Y

Can’t use with vendor Y

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Advantages/disadvantages of soft/firm cores Advantages/disadvantages of soft/firm cores

Soft cores

Can be synthesized to nearly any technology

Can optimize for particular use

– E.g., delete unused portion of core

E.g., delete unused portion of core

Lower power, smaller designs

e po e , s

a e des g s

e po e , s

a e des g s

Requires more design effort

May not work in technology not tested for

May not work in technology not tested for N t ti i d h d f N t ti i d h d f

Not as optimized as hard core for same processor

Firm cores

Compromise between hard and soft cores

– Some

Some retargetability retargetability

– Limited optimization

Limited optimization Better predictability/ease of use Better predictability/ease of use

– Better predictability/ease of use

Better predictability/ease of use

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SLIDE 13

Core Types (cont’d) Core Types (cont’d)

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SLIDE 14

Comparison of Different IP Formats Comparison of Different IP Formats

IP Format Representation Optimization Technology Reusability Hard GDSII Very High Technology Dependent Low Soft RTL Low Technology Independent Very High Firm Targeted Netlist High Technology High Firm Targeted Netlist High Technology Generic High

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SLIDE 15

Benefits of Licensing over Designing IPs Benefits of Licensing over Designing IPs

1.

1. Lack of expertise in designing application

Lack of expertise in designing application-

specific

specific reusable building blocks. reusable building blocks. g

2.

2. Savings in time and cost to produce more complex

Savings in time and cost to produce more complex designs when using third designs when using third-

party IP cores.

party IP cores. g g g g p y p y

3.

3. Ease of integration for available IP cores into more

Ease of integration for available IP cores into more complicated systems. complicated systems.

4.

4. Commercially available IP cores are pre

Commercially available IP cores are pre-

verified and

verified and reduce the design risk. reduce the design risk.

5.

5. Significant improvement to the product design cycle.

Significant improvement to the product design cycle.

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Guidelines for Outsourcing IP Cores Guidelines for Outsourcing IP Cores

Outsource IPs from a well

Outsource IPs from a well-

known IP provider with large

known IP provider with large customer base and great track record. customer base and great track record.

Evaluate the IP functionality using demos and executable

Evaluate the IP functionality using demos and executable models before purchasing. models before purchasing.

Executable models allow you to change parameters and make sure

Executable models allow you to change parameters and make sure the IP provides expected functional results for your design. the IP provides expected functional results for your design.

Ask for a full verification test environment.

A set of models for different stimuli to verify the IP functionality

A set of models for different stimuli to verify the IP functionality.

IPs should be accompanied by detailed documentation.

data sheet, user manuals, simulation and reuse models, test

data sheet, user manuals, simulation and reuse models, test benches and technology migration guidelines benches and technology migration guidelines

Become familiar with the interfaces and functionality of the

utsourced IP.
utsourced IP.
utsou ced
utsou ced

Agreement with IP provider for technical support during the

Agreement with IP provider for technical support during the integration process. integration process.

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SLIDE 17

Business Model for IP Core Providers Business Model for IP Core Providers

Pricing models:

Past

– – Vendors sold product as IC to designers

Vendors sold product as IC to designers

– – Designers must buy any additional copies

Designers must buy any additional copies

Could not (economically) copy from original

Today

– – Vendors can sell as IP

Vendors can sell as IP

– – Designers can make as many copies as needed

Designers can make as many copies as needed

Vendor can use different pricing models

– – Royalty

Royalty-based model based model Royalty Royalty based model based model

Similar to old IC model

Designer pays for each additional model

Fixed price model Fixed price model

– – Fixed price model

Fixed price model

One price for IP and as many copies as needed

– – Many other models used

Many other models used

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SLIDE 18

IP Protection IP Protection

Past

Illegally copying IC very difficult

– Reverse engineering required tremendous, deliberate effort

Reverse engineering required tremendous, deliberate effort

– “Accidental” copying not possible

“Accidental” copying not possible

Today

Cores sold in electronic format

– Deliberate/accidental unauthorized copying easier

Deliberate/accidental unauthorized copying easier

– Safeguards greatly increased

Safeguards greatly increased

– Contracts to ensure no copying/distributing

Contracts to ensure no copying/distributing

– Encryption techniques

Encryption techniques

limit actual exposure to IP

– Watermarking

Watermarking

determines if particular instance of processor was copied

whether copy authorized

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SLIDE 19

New Challenges to Users New Challenges to Users

Licensing arrangements

Not as easy as purchasing IC

More contracts enforcing pricing model and IP protection

– Possibly requiring legal assistance

Possibly requiring legal assistance

Extra design effort

Extra design effort Extra design effort Extra design effort

Especially for soft cores

– Must still be synthesized and tested

Must still be synthesized and tested Minor differences in synthesis tools can cause problems Minor differences in synthesis tools can cause problems

– Minor differences in synthesis tools can cause problems

Minor differences in synthesis tools can cause problems

Verification requirements more difficult

Extensive testing for synthesized soft cores and soft/firm cores

Extensive testing for synthesized soft cores and soft/firm cores d t ti l t h l d t ti l t h l mapped to particular technology mapped to particular technology

– Ensure correct synthesis

Ensure correct synthesis

– Timing and power vary between implementations

Timing and power vary between implementations

E l ifi ti iti l E l ifi ti iti l

Early verification critical

– Cores buried within IC

Cores buried within IC

– Cannot simply replace bad core

Cannot simply replace bad core

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Issues in Synthesizing Soft Cores Issues in Synthesizing Soft Cores y g y g

Synthesis

Synthesis performed by the performed by the core user. core user.

However synthesis

However, synthesis

However, synthesis process depends on process depends on the core provider the core provider d th t h l d th t h l and the technology and the technology provider. provider.

Challenges for core

Challenges for core users: users:

1. 1.

Handling tool Handling tool-

dependent constructs in the core description.

dependent constructs in the core description.

2

H dli t d H dli t d ll ll

2. 2.

Handling unsupported Handling unsupported megacells megacells. .

3. 3.

Handling technology Handling technology-

dependent constraints.

dependent constraints.

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SLIDE 21

Actual Implementation Process for a Soft Core Actual Implementation Process for a Soft Core p

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SLIDE 22

IP Core Classes IP Core Classes

3

3 classes: classes:

1

Digital IP Digital IP

1.

1. Digital IP

Digital IP

2.

2. Analog IP,

Analog IP,

3

Programmable IP Programmable IP

3.

3. Programmable IP

Programmable IP

Digital IP design process:

1.

1. Specification and documentation of the reusable IP;

Specification and documentation of the reusable IP;

2

Implementation using standardized coding practices; Implementation using standardized coding practices;

2.

2. Implementation using standardized coding practices;

Implementation using standardized coding practices;

3.

3. Full verification including code coverage and behavioral

Full verification including code coverage and behavioral (or functional) coverage (or functional) coverage (or functional) coverage. (or functional) coverage.

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SLIDE 23

Analog IP Analog IP

AMS design: ad

AMS design: ad-

hoc custom design process

hoc custom design process

⇒ More time

More time-consuming to develop consuming to develop

⇒ More time

More time consuming to develop consuming to develop

Productivity of AMS design can be improved using a

Productivity of AMS design can be improved using a mixed mixed-

signal

signal SoC SoC design flow, employing AMS IP. design flow, employing AMS IP. g g p y g g p y g

AMS IP must provide more flexibility in design parameters

AMS IP must provide more flexibility in design parameters and performance characteristics and performance characteristics w.r.t w.r.t. digital IP. . digital IP.

Because design specs varies widely between applications,

performance of AMS IPs is significantly influenced by

performance of AMS IPs is significantly influenced by parasitics parasitics and interactions with the surrounding environment and interactions with the surrounding environment and interactions with the surrounding environment. and interactions with the surrounding environment.

⇒ Mostly delivered in the form of hard IP and targeted to one

Mostly delivered in the form of hard IP and targeted to one application in a specific fabrication technology. application in a specific fabrication technology.

– – not easily migrated to other applications/technologies by end

not easily migrated to other applications/technologies by end user. user.

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SLIDE 24

Analog IP (cont’d) Analog IP (cont’d)

Hard IP reduces design cycle significantly when the

Hard IP reduces design cycle significantly when the specifications and fabrication processes are identical specifications and fabrication processes are identical p p p p

But not if it has to be modified, or migrated to a new process.

Firm IP: the most appropriate format to deliver the AMS IP library

Firm IP: the most appropriate format to deliver the AMS IP library components. components.

– – Firm IP captures suitable schematics of the analog blocks

Firm IP captures suitable schematics of the analog blocks with parameters that are adjustable to optimize the design for with parameters that are adjustable to optimize the design for pa a e e s a a e adjus ab e o op e e des g

pa a

e e s a a e adjus ab e o op e e des g

specific applications.

specific applications.

– – Allows ease of migration of IP from foundry to foundry,

Allows ease of migration of IP from foundry to foundry, customer to customer and application to application customer to customer and application to application customer to customer, and application to application. customer to customer, and application to application.

Verification of mixed

Verification of mixed-

signal

signal SoCs SoCs requires requires cosimulation cosimulation

f analog and digital behavioral models to reduce
f analog and digital behavioral models to reduce
f analog and digital behavioral models to reduce
f analog and digital behavioral models to reduce

simulation costs. simulation costs.

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SLIDE 25

Analog IP (cont’d) Analog IP (cont’d)

Requirements for a successful IP block:

should be parameterized,

easily verified through reusable test benches,

well documented,

contain associated views to ease the design process.

– – a behavioral/analytical view (in AMS

a behavioral/analytical view (in AMS-

HDL),

HDL), a parameterized schematic view (transistor level) a parameterized schematic view (transistor level)

– – a parameterized schematic view (transistor level),

a parameterized schematic view (transistor level),

– – a layout view (floor plan).

a layout view (floor plan).

test benches are needed to validate the performance under

test benches are needed to validate the performance under p different operating conditions and at various process corners. different operating conditions and at various process corners.

– – Used as the basis for verification of specifications and for

Used as the basis for verification of specifications and for exploration of the design space for the system exploration of the design space for the system exploration of the design space for the system. exploration of the design space for the system.

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SLIDE 26

Programmable IP Programmable IP

The key to programmable

The key to programmable SoC SoC designs: provide some designs: provide some form of flexible form of flexible

hardware (using programmable logic cores ) and/or

software (using an embedded processor)

infrastructure, often called the programmable fabric. infrastructure, often called the programmable fabric.

Components of programmable logic cores (hardware):

Programmable logic elements,

Programmable interconnect,

Programmable interconnect, Fl ibl Fl ibl

Flexible memory arrays,

Dedicated arithmetic blocks,

High

High-speed communication blocks. speed communication blocks.

High

High speed communication blocks. speed communication blocks.

Hardware programmable core can be soft or hard IP.

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SLIDE 27

Programmable IP (cont’d) Programmable IP (cont’d)

Software Programmability:

use of libraries of code and data structures, along

use of libraries of code and data structures, along with off with off-the the-

use of libraries of code and data structures, along

use of libraries of code and data structures, along with off with off the the shelf shelf kernel kernel and real and real-

time operating systems (RTOSs

time operating systems (RTOSs) to ) to improve improve productivity. productivity.

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SLIDE 28

Differences in Design Between IC and IP Differences in Design Between IC and IP

Limitation of IC design

Number of I/O pins

Design and implement all the functionality in the silicon

Soft IP

Soft IP

No limitation on number of I/O pins

Design all the functionality in HDL code, implement desired parts

Design all the functionality in HDL code, implement desired parts in silicon in silicon in silicon in silicon

IP compiler/Generator: select what you want !!

More high level auxiliary tools to verify design

More difficult in chip

More difficult in chip-

level verification

level verification

Hard IP

Hard IP

No limitation on number of I/O pins

Provide multiple level abstract model

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Design and Implement all the functionality in the layout

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