[PPT] - SoC SoC Design Design Lecture 2: Design Methodology and Lecture PowerPoint Presentation

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SoC SoC Design Design

Lecture Lecture 2: Design Methodology and : Design Methodology and Lecture Lecture 2: Design Methodology and : Design Methodology and Strategies Strategies

Shaahin Hessabi Shaahin Hessabi Department of Computer Engineering Department of Computer Engineering Sharif University of Technology Sharif University of Technology

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Design Challenge Design Challenge

System complexity is increasing

System complexity is increasing P d t lif ti i d i P d t lif ti i d i

Product lifetime is decreasing

⇒ Design efficiency is essential

Design efficiency is essential New design methods are necessary New design methods are necessary

⇒ New design methods are necessary

New design methods are necessary

⇒ Higher abstraction levels are introduced

Higher abstraction levels are introduced

⇒ CAD tools able to handle large amounts of data are needed

CAD tools able to handle large amounts of data are needed g

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Design Methodology Design Methodology g gy g gy

1. 1.

Budget ($, speed, area, power, Budget ($, speed, area, power, schedule, risk) schedule, risk)

2. 2.

Low Low-

level building blocks, high

level building blocks, high-

l

l hit t l l hit t level architecture level architecture

3. 3.

Specification Specification B h i l d i ifi ti B h i l d i ifi ti

4. 4.

Behavioral design, verification Behavioral design, verification

5. 5.

Logic design, verification Logic design, verification L ifi i L ifi i

6. 6.

Layout, verification Layout, verification

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Modern Digital Systems Engineering Modern Digital Systems Engineering

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Coping with Complexity Coping with Complexity p g p y p g p y

How to design complex systems?

How to design complex systems?

1. 1.

Design Partitioning, Abstraction Design Partitioning, Abstraction

2. 2.

Structured Design Structured Design

Design and verification Design and verification dominate escalating dominate escalating project costs project costs

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Abstraction Levels Abstraction Levels

Architecture

Architecture: User’s perspective, what does it do? : User’s perspective, what does it do?

I t ti t i t I t ti t i t

Instruction set, registers

MIPS, x

MIPS, x86 86, Alpha, PIC, ARM, … , Alpha, PIC, ARM, …

Microarchitecture

Microarchitecture (RTL) (RTL)

Microarchitecture

Microarchitecture (RTL) (RTL)

Single cycle, multi

Single cycle, multi-

cycle, pipelined, superscalar?

cycle, pipelined, superscalar?

Logic

Logic: how are functional blocks constructed : how are functional blocks constructed

Logic

Logic: how are functional blocks constructed : how are functional blocks constructed

Ripple carry, carry look

Ripple carry, carry look-

ahead, carry select adders

ahead, carry select adders

Circuit

Circuit: how are transistors used : how are transistors used

Complementary CMOS, pass transistors, domino

Physical

Physical: chip layout : chip layout

Datapaths

Datapaths, memories, random logic , memories, random logic

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Abstraction Levels Abstraction Levels Abstraction Levels Abstraction Levels

Design domains are divided in several abstraction levels:

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Abstraction: System Level Abstraction: System Level y

Highest abstraction level

Description with HDLs or graphical block diagrams

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Abstraction: Abstraction: Microarchitecture Microarchitecture Level Level

Register transfer system is a pure sequential machine

Register transfer system is a pure sequential machine R i t t f i l t ifi ti h t R i t t f i l t ifi ti h t

Register transfer is a complete specification on what a

Register transfer is a complete specification on what a chip will do on every cycle chip will do on every cycle Microarchitecture Microarchitecture components: components:

Microarchitecture

Microarchitecture components: components:

Functional

unctional units units

adder, multiplier,

adder, multiplier, comparator, ALU, etc. comparator, ALU, etc.

Memory

emory elements elements

latch, FF, register, register

latch, FF, register, register-

fil

RAM ROM fil RAM ROM file, RAM, ROM ... file, RAM, ROM ...

Interconnection

nterconnection units units b lti l b lti l

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bus, multiplexer

bus, multiplexer

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Abstraction: Logic Level Abstraction: Logic Level g

Circuit description on a quite low abstraction level

Today only used to design optimized functional blocks

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Abstraction: Circuit Level Abstraction: Circuit Level

Lowest abstraction level

Transistor schematic or mask

Transistor schematic or mask-

layout

layout

Comparable to machine code in computer science

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Abstraction Domains Abstraction Domains

Designs can be performed in

Designs can be performed in 3 3 abstraction domains: abstraction domains:

B h i l d i B h i l d i

Behavioral domain

Structural domain

Physical domain

Each domain gives different freedoms to the designer

Parallel or serial algorithms

Parallel or serial algorithms g

Logic technology and bit

Logic technology and bit-

slice

slice

Full

Full-

custom and macro

custom and macro-

cells ...

cells ...

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Abstraction Domains: Y Abstraction Domains: Y-

Chart

Chart

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Behavioral Domain Behavioral Domain

Abstract function: Description and verification of first ideas

Description and verification of first ideas

Function, and not implementation, is asked

Modeling with general purpose languages

modula

modula-

2

2, , pascal pascal, c, , c, c++ c++, lisp, ... , lisp, ...

matlab

matlab, , mathematica mathematica, ... , ... hdl hdl erilog erilog hdl hdl cathedral cathedral

vhdl

vhdl, , verilog verilog-hdl hdl, cathedral, ... , cathedral, ...

graphic languages as

graphic languages as vee vee, ... , ...

T f ti t T f ti t

Transformation to

Transformation to structural domain: structural domain: synthesis synthesis synthesis synthesis

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Structural Domain Structural Domain

Interconnection of parts: description and verification of a

Interconnection of parts: description and verification of a solution solution solution solution

Restrictions like delay, signal strength, etc.

Modeling styles

vhdl

vhdl, , verilog verilog-

hdl

hdl, ,

schematic

Transformation to physical

Transformation to physical domain: logic minimization domain: logic minimization domain: logic minimization, domain: logic minimization, place and route tools place and route tools

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Physical Domain Physical Domain y

Physical objects with size and positions: description and

description and verification of physical implementation verification of physical implementation

Technology specific implementation

Floorplan

Floorplan, mask , mask-

layout, packaging

layout, packaging

Description formats

cif

cif, gds , gds2 2

stick diagrams, symbolic layout

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Design Strategies Design Strategies g g g g

The goal is a fast as possible

The goal is a fast as possible transfer of an idea to a chip transfer of an idea to a chip

Descriptions in the

Descriptions in the 3 3 abstraction abstraction d i d i domains domains

Structured strategies used:

Hierarch Hierarch

Hierarchy

Regularity

Modularity

Locality

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Design Strategies: Hierarchy Design Strategies: Hierarchy g g y g g y

Hierarchy

Hierarchy: divide and conquer : divide and conquer

Recursively divide system into modules

Dividing in modules, sub

Dividing in modules, sub-

modules until complexity of

modules until complexity of sub sub-modules is comprehensible modules is comprehensible sub sub modules is comprehensible modules is comprehensible

Comparison to software engineering: split programs in

Comparison to software engineering: split programs in modules, procedures, subroutines. modules, procedures, subroutines.

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Design Strategies: Regularity Design Strategies: Regularity g g g y g g g y

Regularity: reuse modules wherever

Regularity: reuse modules wherever possible (similar sub possible (similar sub-

modules)

modules)

Goal: reduction of complexity

Idea: divide in similar building blocks

identical blocks, sub

identical blocks, sub-

blocks, cells, transistor sizes

blocks, cells, transistor sizes 1 dimentional dimentional arra s arra s bit bit slice techniq e slice techniq e

1-dimentional

dimentional arrays arrays: bit : bit-slice technique slice technique

2-

dimentional arrays: systolic arrays

dimentional arrays: systolic arrays

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Design Strategies: Modularity Design Strategies: Modularity g g y g g y

Define sub

Define sub-

modules unambiguously with well

modules unambiguously with well-

defined

defined interfaces interfaces

Allows modules to be treated as black boxes

Diff t d l h ld t i fl h th Diff t d l h ld t i fl h th

Different modules should not influence each other

sub

sub-

modules with well formed interfaces:

modules with well formed interfaces:

do not se transmission gates do not se transmission gates

do not use transmission gates

well defined signal types and strengths

well defined interconnection widths, etc.

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Design Strategies: Locality Design Strategies: Locality g g y g g y

Max local connections, keeping critical paths

Max local connections, keeping critical paths ithi d l b d i ithi d l b d i within module boundaries within module boundaries

Physical and temporal

Physical and temporal Ti l lit l d t h d i ( l l Ti l lit l d t h d i ( l l

Time locality leads to synchronous designs (compare local

Time locality leads to synchronous designs (compare local variables in software engineering) variables in software engineering)

Idea: reduction of complexity due to information hiding

Few global variables

reduction of inter

reduction of inter-module influences module influences

reduction of global wiring

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Automatic Synthesis Automatic Synthesis y

Automatic synthesis: transformation of a design from

Automatic synthesis: transformation of a design from behavioral to structural domain behavioral to structural domain

Silicon

Silicon compilation: transformation compilation: transformation from from behavioral to behavioral to h i l d i h i l d i physical domain physical domain

Synthesis

ynthesis is a design is a design process and not a only a process and not a only a process and not a only a process and not a only a coding as in software coding as in software engineering engineering engineering engineering

Synthesis steps:

Allocation

Scheduling

Binding

inding

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Binding

inding

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Allocation Allocation

Allocation defines the necessary resources

Clocking strategy pipelining memory structure etc have

Clocking strategy, pipelining, memory structure, etc. have

Clocking strategy, pipelining, memory structure, etc. have to be defined to be defined

Manual allocation reduces the search space of design

Manual allocation reduces the search space of design solutions solutions

Trade

rade off between chip

ff between chip

Trade

rade-off between chip

ff between chip-

area and performance area and performance

Parallel implementations of

Parallel implementations of designs have high designs have high throughput, but consume throughput, but consume large areas large areas large areas large areas

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Allocation: RTL Example Allocation: RTL Example p

x = a + b; x = a + b; y = a * c; y = a * c; z = x + d; z = x + d; x = y x = y -

d;

d; x = x + c; x = x + c;

Allocation:

Allocation: 1 1 adder, adder, 1 1 multiplier, multiplier, 1 1 substractor substractor

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Scheduling Scheduling

Scheduling defines the operation sequencing

Operations are bound to clock cycles

Scheduling principles:

R li it d i t f R li it d i t f

Operations are bound to clock cycles

Resource limited: given a set of

Resource limited: given a set of resources, solutions for a resources, solutions for a minimal execution time has to be minimal execution time has to be found found

Time

Time-

limited: given a total

limited: given a total execution time, a minimal set of execution time, a minimal set of execution time, a minimal set of execution time, a minimal set of resources has to be found resources has to be found

Directed acyclic graphs can be

Directed acyclic graphs can be used used

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Binding Binding

Binding phase: operations and memory accesses within

Binding phase: operations and memory accesses within the clock cycles are bound to the hardware resources the clock cycles are bound to the hardware resources the clock cycles are bound to the hardware resources the clock cycles are bound to the hardware resources

Resources can be reused in different clock cycles

Binding steps:

variables are bound to memory elements

perations are bound to functional blocks
perations are bound to functional blocks

p

interconnection elements are bound for data transfers (buses,

interconnection elements are bound for data transfers (buses, multiplexers) multiplexers)

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Binding: Example Binding: Example g p g p

Example:

Example: temporary variables x temporary variables x1 and x and x2 are not used simultaneously are not used simultaneously

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