SoC Design SoC Design g Lecture 4: Programmable ASICs L Lecture - PowerPoint PPT Presentation

SoC Design SoC Design g Lecture 4: Programmable ASICs L Lecture 4: Programmable ASICs L 4 P 4 P bl ASIC bl ASIC Shaahin Hessabi Shaahin Hessabi Department of Computer Engineering Department of Computer Engineering Sharif University of Technology Sharif University of Technology

Programmability Comparison Programmability Comparison g g y y p p � Processors Processors � All programmability in the program All programmability in the program (instructions) stored in memory (instructions) stored in memory � ASICs � ASICs ASICs ASICs � No programmability No programmability � FPGAs � FPGAs FPGAs FPGAs � Device Device- -wide (re)programmability wide (re)programmability Slide Slide 2 2 of of 52 52 Sharif University of Technology Programmable ASICs

Programmable Logic Devices Programmable Logic Devices og og b e b e og c og c ev ces ev ces PROM PROM PAL PAL PLA PLA fixed connection fixed connection programmable connection programmable connection Slide Slide 3 3 of of 52 52 Sharif University of Technology Programmable ASICs

How to Program PLDs? How to Program PLDs? g +5V AND Plane Inputs . . . . OR OR Plane . Outputs +5V . . PLA NOR structure PLA NOR structure (one plane shown) (one plane shown) Slide Slide 4 4 of of 52 52 Sharif University of Technology Programmable ASICs

How to expand PLD architecture? How to expand PLD architecture? � Increase # of inputs/outputs in a conventional PLD? Increase # of inputs/outputs in a conventional PLD? � Problems: � Problems: Problems: Problems: n times the number of inputs and outputs requires n 2 as much � n times the number of inputs and outputs requires n as much chip area � too costly chip area too costly � logic gets slower as number of inputs to AND array increases logic gets slower as number of inputs to AND array increases � Solution: multiple PLDs (i.e., CPLD) with a relatively Solution: multiple PLDs (i.e., CPLD) with a relatively small programmable interconnect. small programmable interconnect. ll ll bl bl i t i t t t � Less general than a single large PLD, but can use software Less general than a single large PLD, but can use software “fitter” to partition into smaller PLD blocks. “fitter” to partition into smaller PLD blocks. fitter to partition into smaller PLD blocks. fitter to partition into smaller PLD blocks. Slide Slide 5 5 of of 52 52 Sharif University of Technology Programmable ASICs

CPLD vs. FPGA CPLD vs. FPGA � CPLD architecture: CPLD architecture: � Small number of large PLDs on a single � Small number of large PLDs on a single Small number of large PLDs on a single Small number of large PLDs on a single chip chip � Programmable interconnect between Programmable interconnect between PLDs PLDs � FPGA architecture: � FPGA architecture: FPGA architecture: FPGA architecture: � Much larger number of smaller Much larger number of smaller programmable logic blocks programmable logic blocks � Embedded in a sea of lots of Embedded in a sea of lots of programmable interconnects programmable interconnects Slide Slide 6 6 of of 52 52 Sharif University of Technology Programmable ASICs

Benefits of FPGAs over ASICs and Processors Benefits of FPGAs over ASICs and Processors � Processors Processors � Slow Slow � Power hungry Power hungry � ASICs ASIC ASIC ASICs � Very expensive Very expensive � Long production cycles � Long production cycles Long production cycles Long production cycles � Upgradeability a major problem Upgradeability a major problem � FPGAs FPGAs � Ideal case: combine the best sides of Ideal case: combine the best sides of hardware and software… hardware and software… � …unfortunately ideal cases rarely exist! …unfortunately ideal cases rarely exist! Slide Slide 7 7 of of 52 52 Sharif University of Technology Programmable ASICs

FPGAs FPGAs � FPGAs are closer to “programmable ASICs” FPGAs are closer to “programmable ASICs” -- -- large large emphasis on interconnection routing emphasis on interconnection routing p p g g � Timing is difficult to predict Timing is difficult to predict -- -- multiple hops vs. the fixed delay of multiple hops vs. the fixed delay of a CPLD’s switch matrix. a CPLD’s switch matrix. � But more “scalable” to large sizes. But more “scalable” to large sizes. “ � FPGA programmable logic blocks have only a few inputs FPGA programmable logic blocks have only a few inputs and 1 and and 1 and 1 or 1 or or 2 or 2 2 flip 2 flip flip flops but there are a lot more of them flip-flops, but there are a lot more of them flops but there are a lot more of them flops, but there are a lot more of them compared to the number of compared to the number of macrocells macrocells in a CPLD. in a CPLD. � Key question: � Key question: Key question: Key question: � How to make logic blocks programmable? How to make logic blocks programmable? � How to connect the wires? How to connect the wires? after after the chip has been fabricated? the chip has been fabricated? Slide Slide 8 8 of of 52 52 Sharif University of Technology Programmable ASICs

FPGA Technologies FPGA Technologies � Static RAM Cells: Static RAM Cells: � The programmable connections are made using pass transistors, � The programmable connections are made using pass transistors, transmission gates, or multiplexers that are controlled by SRAM cells. � Advantage: allows fast in-circuit reconfiguration. � Advantage: allows fast in circuit reconfiguration � Disadvantage: size of the chip required by the RAM technology. � Anti � Anti Anti-fuse: Anti fuse: fuse: fuse: � Anti-fuse resides in a high-impedance state. Can be programmed into low-impedance or "fused" state. � Less expensive than the RAM technology. � One-Time Programmable (OTP) � EPROM/EEPROM transistors: EPROM/EEPROM t EPROM/EEPROM t EPROM/EEPROM transistors: i t i t � Can be reprogrammed without external storage of configuration. � EPROM transistors cannot be re-programmed in-circuit. � EPROM transistors cannot be re-programmed in-circuit Slide Slide 9 9 of of 52 52 Sharif University of Technology Programmable ASICs

SRAM SRAM Static RAM cells are used for three purposes: Static RAM cells are used for three purposes: � As lookup tables (LUTs) for implementing logic. As lookup tables (LUTs) for implementing logic. As lookup tables (LUTs) for implementing logic As lookup tables (LUTs) for implementing logic 1. 1. 1 As embedded RAM blocks (for buffer storage, etc.). As embedded RAM blocks (for buffer storage, etc.). 2. 2. As control to routing and configuration switches. As control to routing and configuration switches As control to routing and configuration switches As control to routing and configuration switches. 3 3. 3. Advantages: Advantages: � Easily changeable (even dynamic reconfiguration) Easily changeable (even dynamic reconfiguration) Easily changeable (even dynamic reconfiguration) Easily changeable (even dynamic reconfiguration) � � Good density Good density � Track latest SRAM technology (moving even faster than Track latest SRAM technology (moving even faster than � technology for logic) technology for logic) Flexible – Flexible – not only good for FSM, also good for arithmetic circuits not only good for FSM, also good for arithmetic circuits � Disad antages Disad antages Disadvantages: Disadvantages: � Volatile Volatile � Generally high power Generally high power Generally high power Generally high power � � Slide Slide 10 10 of of 52 52 Sharif University of Technology Programmable ASICs

SRAM Programming Technology SRAM Programming Technology g g g g gy gy � The pass gate: making a connection between two wire The pass gate: making a connection between two wire segments segments � The multiplexer: connecting the state of the SRAM cells The multiplexer: connecting the state of the SRAM cells to the select lines to the select lines Slide Slide 11 11 of of 52 52 Sharif University of Technology Programmable ASICs

SRAM- SRAM -Controlled Switches Controlled Switches SRAM SRAM Logic L L Logic i i Logic L L Logic i i Cell Cell Cell Cell SRAM SRAM SRAM SRAM Logic Logic Logic Logic Cell Cell Cell Cell Slide Slide 12 12 of of 52 52 Sharif University of Technology Programmable ASICs