[PPT] - SoC SoC Design Design g Lecture L Lecture 3: Introduction to PowerPoint Presentation

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SoC SoC Design Design g

L 3 I d i ASIC I d i ASIC Lecture Lecture 3: Introduction to ASICs : Introduction to ASICs

Shaahin Hessabi Shaahin Hessabi Department of Computer Engineering Department of Computer Engineering Sharif University of Technology Sharif University of Technology

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IC Technology IC Technology

The term

The term ASIC ASIC is often reserved for is often reserved for circuits that are fabricated in a silicon circuits that are fabricated in a silicon circuits that are fabricated in a silicon circuits that are fabricated in a silicon foundry, while circuits that can be foundry, while circuits that can be programmed at the customer’s site programmed at the customer’s site programmed at the customer s site programmed at the customer s site are called Programmable Logic. are called Programmable Logic.

The term

The term full custom full custom is reserved for is reserved for circuits where all silicon layers can circuits where all silicon layers can be optimized. This implies a long be optimized. This implies a long d i d th f ll t d i d th f ll t design process and thus full custom design process and thus full custom is mainly used for high is mainly used for high-

volume high

volume high-

end circuits

end circuits end circuits. end circuits.

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What is an ASIC? What is an ASIC?

An ASIC (Application Specific Integrated Circuit) is an

An ASIC (Application Specific Integrated Circuit) is an integrated circuit for a specific application and (generally) integrated circuit for a specific application and (generally) integrated circuit for a specific application and (generally) integrated circuit for a specific application and (generally) produced in relatively small volumes (batches of produced in relatively small volumes (batches of 10 10 to to 10000 10000 units). units). 10000 10000 units). units).

A typical ASIC is a circuit, where functions are designed

A typical ASIC is a circuit, where functions are designed by the customer, and layout and the fabrication is done by the customer, and layout and the fabrication is done y , y y , y by the silicon vendor. by the silicon vendor.

An ASIC technology helps to shorten the design time by

An ASIC technology helps to shorten the design time by providing a semi providing a semi-

fabricated integrated circuit.

fabricated integrated circuit.

Not ASICs: General

Not ASICs: General-

purpose processors, memory chips

purpose processors, memory chips and other standard components. and other standard components.

Sharif University of Technology Page 3 Introduction to ASICs

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ASIC Vs. Standard IC ASIC Vs. Standard IC

Standard ICs: ASICs: ASICs:

G d i f i ll l

Typically low component cost
Parts available off the shelf
Proven component reliability

Good security of intellectual property Optimum system design Relatively efficient use of board space

Proven component reliability
Multiple sourcing
System house not required to have

y p (smaller systems)

Reliability enhanced at system level

(fewer components) y q in-house experts in chip design

Examples: chipsets, telecom ICs,

i f IC l i IC ( ewe co po e ts)

Performance may be better than

comparable standard ICs (unique features and lower power consumption) processors, interface ICs, logic ICs, memory circuits. features and lower power consumption)

Reduced cost for storage (less

components to store)

D i

t i hi h d d i l i

Design cost is high and design cycle is

long

Sharif University of Technology Page 4 Introduction to ASICs

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ASICs Advantages and Disadvantages ASICs Advantages and Disadvantages g g g g

Advantages Advantages

Effi i f b d

Disadvantages Disadvantages

P i l f d i f il P i l f d i f il

Efficient use of board space

(lower final system cost)

P

d t it

Potential for design failure

Not off

Not off-

the

the-

shelf available

shelf available ( p ifi ti d i t ti ( p ifi ti d i t ti

Product security Unique features and fine-tuning

the product (specification, design, testing (specification, design, testing and documentation phases are and documentation phases are needed) needed) the product

Optimized system performance Possible product differentiation

needed) needed)

High unit cost of IC (higher

High unit cost of IC (higher initial costs initial costs of

f development)

development)

Possible product differentiation

p ) p )

Sharif University of Technology Page 5 of 32 Introduction to ASICs

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ASIC vs the Rest ASIC vs the Rest

W Dedicated HW (ASICs)

1000

OPS/mW (ASICs) Reconfigurable Processor/Logic

100

ncy: MO Processor/Logic ASIPs DSPs

10

Efficien DSPs Embedded Processors

1

Energy E Processors

.1

E

Flexibility

Sharif University of Technology Page 6 Introduction to ASICs

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ASIC Tasks and Roles ASIC Tasks and Roles

System Designer, Architect

System Level Functional Specification, Architectural

System Level Functional Specification, Architectural y p , y p , Specification Specification

Performance and Power Consumption Specification

Partitioning across domains

Partitioning across domains – – RF/Analog, Digital, Software RF/Analog, Digital, Software

E i E i

– Estimates

Estimates

Block Level Partitioning, Interfaces

Memory and Interconnect Hierarchy

Power Management Strategy

Chip Level Planning

– Package, Pads, I/O

Package, Pads, I/O Preliminary Floorplan Preliminary Floorplan

– Preliminary Floorplan

Preliminary Floorplan

– Global Control and Timing

Global Control and Timing

– Clock and Reset strategy

Clock and Reset strategy

– DFT Strategy

DFT Strategy DFT Strategy DFT Strategy

Startup and Boot Sequence

Sharif University of Technology Page 7 Introduction to ASICs

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ASIC Tasks and Roles (cont’d) ASIC Tasks and Roles (cont’d)

Logic Designer

Block Level Design

Detailed Block Level Design Specification

Synthesis and hand

Synthesis and hand-

off of a
ff of a timing clean

timing clean block block

Exhaustive block level verification with near perfect code coverage

Verification Engineer

Verification Plan

Modeling of Environment

Verification Environment, Scripts, Regression

DFT E i DFT E i

DFT Engineer

DFT logic

Boundary Scan

ATPG

Sharif University of Technology Page 8 Introduction to ASICs

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ASIC Tasks and Roles (cont’d) ASIC Tasks and Roles (cont’d)

Front end ASIC Engineer

Chip Level

– Synthesis Strategy

Synthesis Strategy

– Synthesis Scripts

Synthesis Scripts

– Timing Analysis

Timing Analysis g y g y

– Interface to backend

Interface to backend

Back end ASIC Engineer

Floorplanning

Place and Route

Clock Tree Synthesis

Power routing

Pads and Package

Integration and Test

Sharif University of Technology Page 9 Introduction to ASICs

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ASIC Project Phases ASIC Project Phases

1. 1.

Requirements Capture Requirements Capture

Market Survey Business Opportunities Customer Interaction

Market Survey, Business Opportunities, Customer Interaction

Requirements Specification

Requirements Specification – – CRS (Customer Requirements CRS (Customer Requirements Specification) Specification)

– Hierarchical list of requirements

Hierarchical list of requirements

– Peformance, Cost and Delivery Schedule

Peformance, Cost and Delivery Schedule

2

PreStudy PreStudy

2. 2.

PreStudy PreStudy

Estimate Die Size, Package, Power Consumption, Performance,

Estimate Die Size, Package, Power Consumption, Performance, Development, Manufacturing, Integration and Test Times Development, Manufacturing, Integration and Test Times

Buy or Develop Decisions

Explore architectural and algorithmic alternatives

Explore architectural and algorithmic alternatives Interact with Customer Marketting and refine Requirements doc Interact with Customer Marketting and refine Requirements doc

Interact with Customer, Marketting and refine Requirements doc.

Quit or go ahead decision

Sharif University of Technology Page 10 Introduction to ASICs

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ASIC Project Phases (cont’d) ASIC Project Phases (cont’d)

3. 3.

System Design System Design I l t ti I l t ti D i d V ifi ti D i d V ifi ti

4. 4.

Implementation Implementation – Design and Verification Design and Verification

5. 5.

Integration & Test Integration & Test

6. 6.

Maintenance Maintenance

Sharif University of Technology Page 11 Introduction to ASICs

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Design Requirements Design Requirements

Technology

Technology-

driven:

driven:

G t C l it G t C l it

Greater Complexity

Higher Density

Increased Performance

Lower Power Dissipation

Market

Market-

driven:

driven:

Shorter Time

Shorter Time-

to

to-

Market (TTM)

Market (TTM)

– – Average TTM constraint is about

Average TTM constraint is about 8 8 months. months.

– – Missing the market window is very costly.

Missing the market window is very costly.

Lower cost

Lower cost Non Non Recurring Engineering (NRE) cost volume sensitive Recurring Engineering (NRE) cost volume sensitive

– – Non

Non-Recurring Engineering (NRE) cost ,volume sensitive Recurring Engineering (NRE) cost ,volume sensitive

– – Manufacturing and test cost

Manufacturing and test cost

Sharif University of Technology Page 12 Introduction to ASICs

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Complexity Complexity

Architecture Efficacy Architecture d Efficacy Gap Trends Design Productivity Methodology Trends y Gap Trends Power Capacity Gap Power Management Trends

Sharif University of Technology Page 13 Introduction to ASICs

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Design criteria Design criteria

Three dimensions: area, delay, power

i d ti i d ti

size, speed, energy consumption

Four dimensions: plus testability (reliability)

Four dimensions: plus testability (reliability) Area: gates wires buses etc Area: gates wires buses etc

Area: gates, wires, buses, etc

Delay: inside a module, between modules, etc

Delay: inside a module, between modules, etc P ti k d t t l P ti k d t t l

Power consumption: average, peak and total

Optimizations: transferring from one dimension to

Optimizations: transferring from one dimension to another another another another

design quality is measured by combined parameters, e.g.,

design quality is measured by combined parameters, e.g., energy consumption per input sample energy consumption per input sample gy p p p p gy p p p p

Sharif University of Technology Page 14 Introduction to ASICs

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Full Full-

Custom ASIC

Custom ASIC

An engineer designs some or all of the logic cells,

An engineer designs some or all of the logic cells, circuits, layout specifically for one ASIC. circuits, layout specifically for one ASIC.

Excellent performance, small size, low power

Demands long design cycle

Demands long design cycle Hi h NRE t Hi h NRE t

High NRE cost

Mostly used:

If no pre

If no pre designed cells are available (e g new or highly designed cells are available (e g new or highly

If no pre

If no pre-designed cells are available (e.g., new or highly designed cells are available (e.g., new or highly specialized circuit) specialized circuit)

When high performance is needed, and e

When high performance is needed, and existing cell libraries are xisting cell libraries are not suitable not suitable

– – Are slow, or not small enough, or consume too much power

Are slow, or not small enough, or consume too much power

Requirements for high

Requirements for high voltage (automobile) mixed analog/digital voltage (automobile) mixed analog/digital

Requirements for high

Requirements for high-voltage (automobile), mixed analog/digital voltage (automobile), mixed analog/digital (communications), or sensors and actuators (communications), or sensors and actuators

Sharif University of Technology Page 15 Introduction to ASICs

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Standard Standard-

Cell ASICs

Cell ASICs

Cell

Cell-

based IC (CBIC)

based IC (CBIC)

U d i d l i ll (k t d d ll ) d i d l i ll (k t d d ll ) d

Use

se predesigned logic cells (known as standard cells) predesigned logic cells (known as standard cells) and and larger cells, called larger cells, called megacells megacells or cores

r cores (e.g. microcontroller

(e.g. microcontroller) )

The standard cell library defines logic elements of varying

The standard cell library defines logic elements of varying y g y g y g y g complexity: SSI, MSI logic, data complexity: SSI, MSI logic, data path blocks, memories and path blocks, memories and system system-

level blocks.

level blocks.

Standard cells are built by someone else using full

Standard cells are built by someone else using full custom custom

Standard cells are built by someone else using full

Standard cells are built by someone else using full-custom custom design techniques design techniques

– – Designers

Designers save time, money, and reduce save time, money, and reduce risk by using a risk by using a predesigned, pretested cell library predesigned, pretested cell library

– – Each

ach standard cell can be optimized individually standard cell can be optimized individually

All

ll mask layers are mask layers are customized ( customized (transistors and interconnect) transistors and interconnect)

All

ll mask layers are mask layers are customized ( customized (transistors and interconnect) transistors and interconnect)

Custom

ustom blocks can be embedded blocks can be embedded

Manufacturing

anufacturing lead time is about lead time is about 2 2 months months

Sharif University of Technology Page 16 Introduction to ASICs

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Standard Standard-

Cell

Cell ASICs (example) ASICs (example) ( p ) ( p )

Cells are configured in rows and have constant height

Cells are configured in rows and have constant height and variable width and variable width and variable width and variable width

A cell library holds

A cell library holds relevant information relevant information about cells about cells

Name, functionality, delays, resistance, capacitance, layout,

Name, functionality, delays, resistance, capacitance, layout, area, pin topology, etc. area, pin topology, etc.

All cells in a library have

All cells in a library have same standardized layouts, same standardized layouts, i.e., all cells have the same i.e., all cells have the same height. height.

Sharif University of Technology Page 17 Introduction to ASICs

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Gate Gate-

Array ASICs

Array ASICs

A gate

A gate-

array chip contains prefabricated adjacent rows of

array chip contains prefabricated adjacent rows of PMOS and NMOS transistors PMOS and NMOS transistors PMOS and NMOS transistors. PMOS and NMOS transistors.

Interconnect is defined by designer and fabricated using a custom

Interconnect is defined by designer and fabricated using a custom mask ( mask (masked gate array or MGA) masked gate array or MGA)

– – Called

Called personalization personalization

Designer chooses cells from a gate

Designer chooses cells from a gate-

array library of predefined,

array library of predefined, pretested cells pretested cells pretested cells pretested cells

Chip is partially fabricated (cells, power, etc. added) and

Chip is partially fabricated (cells, power, etc. added) and then stockpiled then stockpiled then stockpiled then stockpiled

When design is received for fabrication, the remaining metal

When design is received for fabrication, the remaining metal layers are added layers are added

Cheaper

Cheaper — — everyone shares cost of producing high volume of everyone shares cost of producing high volume of initial chip initial chip

Quick turn

Quick turn-around around — days, couple weeks days, couple weeks

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Quick turn

Quick turn around around days, couple weeks days, couple weeks

Page 18 Introduction to ASICs

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Gate Array Features Gate Array Features

+ Low manufacturing cost Low manufacturing cost

Due to the high yield of MPGAs (only

Due to the high yield of MPGAs (only 4 masking steps are masking steps are

Due to the high yield of MPGAs (only

Due to the high yield of MPGAs (only 4 4 masking steps are masking steps are involved in personalization: one for each of the two metal layers involved in personalization: one for each of the two metal layers and two for placing contacts on these layers). and two for placing contacts on these layers).

More metal layers to improve the

More metal layers to improve the routability routability results in lower yield results in lower yield

More metal layers to improve the

More metal layers to improve the routability routability results in lower yield, results in lower yield, thus adversely affects the manufacturing cost thus adversely affects the manufacturing cost

− Difficult layout Difficult layout cu t ayout cu t ayout

Vertical and horizontal channels can accommodate only a fixed

Vertical and horizontal channels can accommodate only a fixed number of wires. number of wires.

Automatic layout generator can easily create congestion by

Automatic layout generator can easily create congestion by trying to place strongly connected cells close, thus exceeding the trying to place strongly connected cells close, thus exceeding the wiring capacity of the channels. wiring capacity of the channels.

Floorplanning

Floorplanning is also difficult because of the rigid array structure. is also difficult because of the rigid array structure. All cells have to be designed to meet the size constraint imposed All cells have to be designed to meet the size constraint imposed by the array structure by the array structure

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by the array structure. by the array structure.

Page 19 Introduction to ASICs

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Gate Array Features (cont’d) Gate Array Features (cont’d)

− Difficult to estimate performance Difficult to estimate performance

B f th li it d ti it it i diffi lt t ti t B f th li it d ti it it i diffi lt t ti t

Because of the limited routing capacity, it is difficult to estimate

Because of the limited routing capacity, it is difficult to estimate the wire delays of gate array designs before routing is done. the wire delays of gate array designs before routing is done.

− Gate count and utilization Gate count and utilization Gate count and utilization Gate count and utilization

Gate utilization is always less than the specified capacity.

– – strongly dependent on the type of design (structured or

strongly dependent on the type of design (structured or random) and the gate array architecture. random) and the gate array architecture.

Gate array capacities come in discrete sizes, typically differing in

Gate array capacities come in discrete sizes, typically differing in 35 35% steps % steps most gate array designs will not utilize the most gate array designs will not utilize the 35 35% steps % steps most gate array designs will not utilize the most gate array designs will not utilize the complete capacity. complete capacity.

Sharif University of Technology Page 20 Introduction to ASICs

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Channeled Channeled Gate Array Gate Array

Only the interconnect is customized

The interconnect uses predefined spaces between rows

f base cells
f base cells

Manufacturing

Manufacturing lead time is between two days and two lead time is between two days and two

Manufacturing

Manufacturing lead time is between two days and two lead time is between two days and two weeks weeks

Sharif University of Technology Page 21 Introduction to ASICs

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Channel Channel-less less Gate Array Gate Array

Also known as sea

Also known as sea-

of
f-
gate (SOG)

gate (SOG) array array

Only

Only some mask layers are customized: the some mask layers are customized: the interconnect interconnect

Cells are connected via unused transistors

no predefined channels (

no predefined channels (over the cell routing)

ver the cell routing)

utilizes the active silicon poorly, but allows higher density of gates.

Manufacturing lead time is between

Manufacturing lead time is between 2 2 days and days and 2 2 weeks weeks

Sharif University of Technology Page 22 Introduction to ASICs

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Field Programmable Gate Arrays Field Programmable Gate Arrays g y g y

None of the mask layers are customized

Basic logic cells and interconnect can be programmed

Basic cells can be SRAM

Basic cells can be SRAM-

based, flash

based, flash-

memory

memory-

based or

based or fuse fuse-based (one time programmable), and based (one time programmable), and can implement can implement fuse fuse based (one time programmable), and based (one time programmable), and can implement can implement combinational, as well as sequential logic combinational, as well as sequential logic

Programmable I/O cells

Programmable I/O cells surround the core surround the core

Sharif University of Technology Page 23 Introduction to ASICs

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Programmable Logic Devices Programmable Logic Devices g g g g

Standard ICs, available in standard configurations, sold in

Standard ICs, available in standard configurations, sold in high volume high volume g g

But can be configured / programmed to create a specialized device

No customized cells or masks, just a single large block of

fast

fast design turnaround design turnaround

a single large block of

a single large block of programmable interconnect programmable interconnect

a single large block of

a single large block of programmable interconnect programmable interconnect

a matrix of logic

a matrix of logic macrocells macrocells that that usually consist of programmable usually consist of programmable array logic followed by a flip array logic followed by a flip-

flop or

flop or latch latch

Sharif University of Technology Page 24 Introduction to ASICs

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Prototyping Prototyping yp g yp g

Possibility to check how a system works at conditions very

Possibility to check how a system works at conditions very close to the operating environment without the need to close to the operating environment without the need to close to the operating environment without the need to close to the operating environment without the need to create expensive chips create expensive chips

XESS Corp., www.xess.com, $ XESS Corp., www.xess.com, $400 400 [ Xilinx Inc., FPGA XC [ Xilinx Inc., FPGA XC2 2S S100 100 ] ] ErST ErST Electronics, www.erst.ch, $ Electronics, www.erst.ch, $3380 3380 [ Xilinx Inc FPGA X [ Xilinx Inc FPGA X2V V2000 2000 ]

Sharif University of Technology Page 25 Introduction to ASICs

[ Xilinx Inc., FPGA X [ Xilinx Inc., FPGA X2V V2000 2000 ]

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Comparison Comparison

Sharif University of Technology Page 26 Introduction to ASICs

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Comparison (cont’d) Comparison (cont’d)

Analogue Analogue Custom Custom logic cells logic cells Custom Custom mask layers mask layers Family Family member member ASIC type ASIC type

A pizza built from A pizza built from Some Some All All Analog/digital Analog/digital Full Full-

custom

custom

logic cells logic cells mask layers mask layers member member

A pizza built from A pizza built from scratch scratch None None All All CBIC CBIC A garden pizza with A garden pizza with predefined predefined selection selection None None Some Some MGA MGA Semicustom Semicustom A frozen pizza A frozen pizza g p g p cheese option cheese option None None None None FPGA FPGA A frozen pizza A frozen pizza None None None None PLD PLD None None None None FPGA FPGA Programmable Programmable

Sharif University of Technology Page 27 Introduction to ASICs

Adapted from professor Robert A. Walker’s (Kent University) VLSI Design course web site Adapted from professor Robert A. Walker’s (Kent University) VLSI Design course web site

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Economics of ASICs Economics of ASICs

In terms of part cost:

FPGA > MGA > CBIC

In terms of product

In terms of product cost: cost:

fixed part cost + variable

fixed part cost + variable cost per part * sales cost per part * sales volumes volumes volumes volumes

Example (using imaginary costs): Example (using imaginary costs): Example (using imaginary costs): Example (using imaginary costs):

FPGA: $
FPGA: $21

21, ,800 800 (fixed) $ (fixed) $39 39 (variable) • MGA: $ (variable) • MGA: $86 86, ,000 000 (fixed) $ (fixed) $10 10 (variable) (variable)

CBIC $
CBIC $146

146, ,000 000 (fixed) $ (fixed) $8 8 (variable) (variable) Then we can calculate the following break Then we can calculate the following break-

even volumes:

even volumes:

FPGA/MGA »
FPGA/MGA » 2000

2000 parts parts

FPGA/CBIC »
FPGA/CBIC » 4000

4000 parts parts

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FPGA/CBIC » FPGA/CBIC » 4000 4000 parts parts

MGA/CBIC »
MGA/CBIC » 20

20, ,000 000 parts parts

Page 28 Introduction to ASICs

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Economics of ASICs Economics of ASICs

ASIC fixed costs

t i i t (EDA t i i t (EDA

training cost (EDA

training cost (EDA tools) tools)

hardware/software cost

design for test

nonrecurring

nonrecurring-

i

i (NRE) t i i (NRE) t engineering (NRE) cost engineering (NRE) cost

– masks

masks

– simulation

simulation

– test program

test program

– software tools

software tools design verification design verification

– design verification

design verification

– prototype samples

prototype samples

Sharif University of Technology Page 29 Introduction to ASICs

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Economics of ASICs Economics of ASICs

ASIC variable

ASIC variable costs costs costs costs

wafer size

wafer cost

gate density

gate utilization

die size

=(#gates/ =(#gates/util util)/density )/density =(#gates/ =(#gates/util util)/density )/density

die per wafer

defect density

yield

die cost

profit margin

profit margin i t i t

price per gate

part cost

Sharif University of Technology Page 30 Introduction to ASICs

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Economics of ASICs Economics of ASICs

For any new process

For any new process technology, the price per technology, the price per

CBICs and MGAs are

CBICs and MGAs are introduced at the same introduced at the same gate decreases by gate decreases by 40 40% in % in the the 1 1st year, st year, 20 20% in the % in the 2nd year and then nd year and then time and price time and price

The

he price of a new price of a new technology is initially technology is initially 2nd year, and then nd year, and then remains constant remains constant

A new process

new process technology is initially technology is initially 10 10% above the process % above the process that it replaces that it replaces technology is introduced technology is introduced every every 2 2 years with feature years with feature size decreasing by a size decreasing by a

FPGAs are introduced

ne year after CBICs
ne year after CBICs

using the same process using the same process size decreasing by a size decreasing by a factor of factor of 2 2 every every 5 5 years. years. using the same process using the same process

Initial

Initial FPGA price is FPGA price is 10 10% % higher than the initial higher than the initial g price for CBICs or MGAs price for CBICs or MGAs using the same process using the same process

Sharif University of Technology Page 31 Introduction to ASICs