A 61.5dB SNDR Pipelined ADC Using Simple Highly-Scalable Ring - - PowerPoint PPT Presentation

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A 61.5dB SNDR Pipelined ADC Using Simple Highly-Scalable Ring - - PowerPoint PPT Presentation

Jun 24, 2023 140 likes •686 views

A 61.5dB SNDR Pipelined ADC Using Simple Highly-Scalable Ring Amplifiers Benjamin Hershberg 1 , Skyler Weaver 1 , Kazuki Sobue 2 , Seiji Takeuchi 2 , Koichi Hamashita 2 , Un-Ku Moon 1 1 Oregon State University, Corvallis, OR, USA 2 Asahi Kasei

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SLIDE 1

A 61.5dB SNDR Pipelined ADC Using Simple Highly-Scalable Ring Amplifiers

Benjamin Hershberg1, Skyler Weaver1, Kazuki Sobue2, Seiji Takeuchi2, Koichi Hamashita2, Un-Ku Moon1

1Oregon State University, Corvallis, OR, USA 2Asahi Kasei Microdevices, Atsugi, Japan

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SLIDE 2

An Incomplete Solution

  • Goal: develop truly scalable amplifiers

– Conventional opamps are fundamentally ill-suited for nanoscale CMOS – Efficiency in amplification-based designs is actually getting worse

  • ADCs

– Amplifier-less ADCs (i.e. SARs) provide excellent scalability for some of the design space – Scalable amplifiers are needed to cover the entire ADC design space

  • The more scalable options we have, the better

2

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SLIDE 3

Beating the Trend

A scalable amplifier must

  • Operate well in nanoscale CMOS
  • Improve with nanoscale CMOS

Circuit level requirements

  • Minimize SNR loss from low-voltage, degrading ro
  • Exploit digital scaling benefits
  • Avoid conventional RC-based settling

3

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SLIDE 4

Beating the Trend

  • VDZ

+ VIN VOUT

Ring Amplifier

(Ringamp, RAMP)

4

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SLIDE 5

Ring Amplification Basic Theory

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SLIDE 6

Ring Amplifier: Basic Theory

  • Basic MDAC test structure

RST

VCMX VIN ±VREF CLOAD

RST RST

VCMO

Example MDAC Feedback Structure

AMP

6

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SLIDE 7

Ring Amplifier: Basic Theory

  • Ring Oscillator
  • Unstable…

…but will oscillate around the correct settled value

RST

VCMX=0.6V VIN ±VREF CLOAD

RST RST

VCMO

Example MDAC Feedback Structure

VIN VOUT

RST

7

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SLIDE 8

1 2 3 4 5 6 0.2 0.4 0.6 0.8 1 1.2 Volts time (ns)

1.2 1 0.8 0.6 0.4 0.2 1 2 3 4 5 6

Volts time (ns)

Ring Oscillator Sample Waveform

VCMX = 0.6V (ideal settled input value)

VIN

8

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SLIDE 9

Ring Amplifier: Basic Theory

RST

VCMX VIN ±VREF CLOAD

RST RST

VCMO

Example MDAC Feedback Structure

  • VDZ

+

RST RST RST

  • VOS+

+VOS-

  • Split signal into two separate paths
  • Embed offset in each path

9

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SLIDE 10

1 2 3 4 5 6 0.2 0.4 0.6 0.8 1 1.2 Volts time (ns)

Ring Amplifier Sample Waveform

VDZ = 0mV

1.2 1 0.8 0.6 0.4 0.2 1 2 3 4 5 6

Volts time (ns)

  • VDZ

+ VAN VIN VOUT VA VBP VBN VAP

10

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SLIDE 11

1 2 3 4 5 6 0.2 0.4 0.6 0.8 1 1.2 Volts time (ns)

Ring Amplifier Sample Waveform

VDZ = 0mV

1.2 1 0.8 0.6 0.4 0.2 1 2 3 4 5 6

Volts time (ns)

  • VDZ

+ VAN VIN VOUT VA VBP VBN VAP

11

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SLIDE 12

1 2 3 4 5 6 0.2 0.4 0.6 0.8 1 1.2 Volts time (ns)

Ring Amplifier Sample Waveform

VDZ = 0mV

1.2 1 0.8 0.6 0.4 0.2 1 2 3 4 5 6

Volts time (ns)

  • VDZ

+ VAN VIN VOUT VA VBP VBN VAP

12

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SLIDE 13

1 2 3 4 5 6 0.2 0.4 0.6 0.8 1 1.2 Volts time (ns)

Ring Amplifier Sample Waveform

VDZ = 0mV

1.2 1 0.8 0.6 0.4 0.2 1 2 3 4 5 6

Volts time (ns)

  • VDZ

+ VAN VIN VOUT VA VBP VBN VAP

13

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SLIDE 14

1 2 3 4 5 6 0.2 0.4 0.6 0.8 1 1.2 Volts time (ns)

Ring Amplifier Sample Waveform

VDZ = 200mV

1.2 1 0.8 0.6 0.4 0.2 1 2 3 4 5 6

Volts time (ns)

Plateaus form at dead-zone crossings

14

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SLIDE 15

1 2 3 4 5 6 0.2 0.4 0.6 0.8 1 1.2 Volts time (ns)

Ring Amplifier Sample Waveform

VDZ = 250mV

1.2 1 0.8 0.6 0.4 0.2 1 2 3 4 5 6

Volts time (ns)

15

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SLIDE 16

1 2 3 4 5 6 0.2 0.4 0.6 0.8 1 1.2 Volts time (ns)

Ring Amplifier Sample Waveform

VDZ = 300mV

1.2 1 0.8 0.6 0.4 0.2 1 2 3 4 5 6

Volts time (ns)

16

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SLIDE 17

1 2 3 4 5 6 0.2 0.4 0.6 0.8 1 1.2 Volts time (ns)

Ring Amplifier Sample Waveform

VDZ = 350mV

1.2 1 0.8 0.6 0.4 0.2 1 2 3 4 5 6

Volts time (ns)

17

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SLIDE 18

1 2 3 4 5 6 0.2 0.4 0.6 0.8 1 1.2 Volts time (ns)

Ring Amplifier Sample Waveform

VDZ = 400mV

1.2 1 0.8 0.6 0.4 0.2 1 2 3 4 5 6

Volts time (ns)

18

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SLIDE 19

1 2 3 4 5 6 0.2 0.4 0.6 0.8 1 1.2 Volts time (ns)

Ring Amplifier Sample Waveform

VDZ = 250mV

1.2 1 0.8 0.6 0.4 0.2 1 2 3 4 5 6

Volts time (ns)

Decreasing VOV reduces slew-rate

19

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SLIDE 20

VOV Dynamic Pinch-off

20

AV2*(VIN*AV1 + VOS) AV2*(VIN*AV1 - VOS)

  • VDZ

+ VIN VOUT

AV1 AV2

+VOS-

  • VOS+
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SLIDE 21

VOV Dynamic Pinch-off

AV2*(VIN*AV1 + VOS) AV2*(VIN*AV1 - VOS)

  • VDZ

+ VIN VOUT

AV1 AV2

+VOS-

  • VOS+

21

– ID decreases

  • VOV → ID

2

– Ro increases

  • Dominant pole → DC
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SLIDE 22

Dynamic Dead-zone Adjustment

  • Initial: AV1 limited by slewing
  • Final: AV1 set by AC small-signal
  • Dynamically adjusts input-referred dead-zone
  • Enhances Speed / Accuracy trade-off

22

  • VDZ

+ VIN

IP-IN IP IN AV1

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SLIDE 23

Core Benefits

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SLIDE 24

Ring Amplifier Core Benefits

Slew-based charging

  • Charges with maximally biased, digitally-switched

current sources

– Can be very small, even for large CLOAD – Decouples internal speed vs. output load requirements

24

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SLIDE 25

Ring Amplifier Core Benefits

Scalability (Speed/Power)

  • Internal speed/power (mostly) independent of CLOAD

– Inverter td, crowbar current, parasitic C’s – Digital power-delay product scaling benefits apply

  • Captures the same power/speed trends as digital circuits

td VDD IAVG PDP = VDD·IAVG·td = Etot DIN DOUT CGS

25

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SLIDE 26

Ring Amplifier Core Benefits

Scalability (Output Swing / SNR)

  • Compression immune: rail-to-rail output swing
  • 50dB: Input-referred dead-zone size will limit accuracy
  • 90dB: dynamic pinch-off effects maintain high accuracy

– weak inversion – saturation even for small VDS – gain-boosting from increased ro

1 2 3 4 5 6 7 0.2 0.3 0.4 0.5 0.6 0.7 0.8 0.9 1 Volts time (ns) Small Swing Medium Swing Large Swing 1 2 3 4 5 6 7 0.55 0.6 0.65 Volts time (ns) Small Swing Medium Swing Large Swing

26

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SLIDE 27

Noise Suppression

  • Output pinch-off reduces ID, gm

– Internal noise sources attenuated

  • Initial charging noisy → final settling quiet

27

  • VDZ

+ VIN VOUT Max VOV

1 2 3

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SLIDE 28

Noise Suppression

  • Output pinch-off reduces ID, gm

– Internal noise sources attenuated

  • Initial charging noisy → final settling quiet

28

  • VDZ

+ VIN VOUT Pinch-off

1 2 3

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SLIDE 29

ADC Implementation Details

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SLIDE 30

Structure Overview

30

  • 10.5b Pipelined ADC

– 9 identical 1.5b MDAC stages – 1.5b Flash

  • Simple proof-of-concept built to characterize:

– Basic functionality – Rail-to-rail output swing – Noise immunity

1.5b

CU = 200 fF

VIN+ VIN- 1.5b

CU = 200 fF

1.5b

CU = 200 fF

1.5b

CU = 200 fF

1.5b

CU = 200 fF

1.5b

CU = 200 fF

1.5b

CU = 200 fF

1.5b

CU = 200 fF

1.5b

CU = 200 fF

1.5b

FLASH

1.5b: 1b + 0.5b redundancy (MDAC gain of 2 per stage) Uses Same Ringamp for all Stages FLASH

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SLIDE 31

Ring amplifier

31

  • Very small, very simple, uses minimum size inverters

VIN VOUT

VRN

ΦS ΦS ΦS

VRP 100fF 100fF 100fF 1X 1X 0.5X 1X 2X 2X 0.5X 1X 1X

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SLIDE 32

Float-sampled MDAC

32

VIN+

RAMP

D·VREF VCMX VOUT+ ФS ФS ФA ФA ФSE ФA ФSE VIN-

RAMP

  • D·VREF

VOUT- ФS ФS ФA ФA ФSE ФA

200fF 200fF 200fF 200fF

  • Differential gain: 2X
  • Common-mode gain: 1X
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SLIDE 33

Measurement Results

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SLIDE 34

Input Spectrum

34

  • Limited by quantization noise
  • Inherent noise advantage demonstrated
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SLIDE 35

Rail-to-Rail Output Swing Test

35 20 25 30 35 40 45 50 55 60

  • 40
  • 35
  • 30
  • 25
  • 20
  • 15
  • 10
  • 5

SNDR (dB) Input Amplitude (dBFS)

Rail-to-rail output swing test

VDD = 1.2V Vrefp = 1.2V Vrefn = 0V fs = 4MHz

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SLIDE 36

Ring Amp Dead-Zone Sensitivity

36 45 50 55 60 65

  • 20

20 40 60 80 100 SNDR (dB) 1st stage dead-zone (mV differential pk-pk)

Ring Amplifier dead-zone sensitivity

nominal value (40mV)

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SLIDE 37

Performance Summary

Technology 0.18µm 1P4M CMOS Resolution 10.5 bits Analog Supply 1.3 V Sampling rate 30 Msps ERBW 15 MHz Input Range 2.2 V pk-pk diff. SNDR 61.5 dB SNR 61.9 dB SFDR 74.2 dB ENOB 9.9 bits Total Power 2.6 mW FoM 90 fJ/c-step

37

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SLIDE 38

Room for improvement

  • Design meant to probe THD, SNR limits of minimum

sized ringamp

– Speed set intentionally low – No optimization, stage scaling – Ringamps left ‘on’ during sampling phase – FoM can easily be improved

  • ISSCC 2012 implementation**

– Speed: 90Msps – Power save features: 50% reduction in power

** B. Hershberg, et al. “Ring Amplifiers for Switched Capacitor Circuits”, ISSCC 2012 38

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SLIDE 39

Scalability Test

  • Design Challenge:

– MDAC for 11b pipelined ADC with 10b ENOB – 130nm, 90nm, 65nm, 45nm, 32nm – ASU predictive technology models [ptm.asu.edu]

39

VDD process defined SNDR > 66dB (input referred) Output Swing 0.8VDD Total Load 800fF Speed proportional to 1/Lmin Power Minimize

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SLIDE 40

Scalability Test

40 VRN

RST

VRP

RST RST

Test Ringamp

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SLIDE 41

Scalability Test

41

VIN+

RAMP

VCM VCMX ФS ФS ФA ФA ФSE VIN-

RAMP

ФS ФS ФA ФA ФSE

200fF 200fF 200fF 200fF 300fF 300fF

ФS ФS

Pesudo-differential Test MDAC

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SLIDE 42

Scalability Test

42

100 150 200 250 300 350 400 10

  • 2

10

  • 1

10

Conversion Speed (MHz) Efficiency (pJ / cycle) PTOT / fs (PTOT - PCV

2f) / fs

130nm 1.2V 100MHz 90nm 1.2V 150MHz 65nm 1.2V 200MHz 45nm 1.05V 300MHz 32nm 1.0V 420MHz

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SLIDE 43

Conclusion

  • Ring Amplification

– High efficiency slew-based charging – Rail-to-rail output swing – Noise advantage – Performance scales with digital process

  • Key Concepts

– Dead-zone – VOV pinch-off – Dynamic gain adjustment

43

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SLIDE 44

Thank you for your attention

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SLIDE 45

Additional Slides

Possibly useful in Q&A afterwards

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SLIDE 46

40 45 50 55 60 65 70 75 80 10 20 30 40 50 dB Input Frequency (MHz)

Performance vs. Input Frequency

SFDR SNR SNDR

Performance vs. Input Frequency

ERBW > 15 MHz

46

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SLIDE 47

SNDR vs. Input Amplitude

47 20 25 30 35 40 45 50 55 60

  • 40
  • 35
  • 30
  • 25
  • 20
  • 15
  • 10
  • 5

SNDR Input Amplitude (dBFS)

SNDR vs Input Amplitude

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SLIDE 48

SNDR vs. Sampling Frequency

48 10 20 30 40 50 60 70 20 40 60 80 100 SNDR (dB) Sampling Frequency (MHz)

SNDR vs Sampling Frequency

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SLIDE 49

INL / DNL

49

200 400 600 800 1000 1200 1400 1600 1800 2000

  • 0.4
  • 0.2

0.2 0.4 0.6 DIFFERENTIAL NONLINEARITY vs. DIGITAL OUTPUT CODE DIGITAL OUTPUT CODE DNL (LSB for 11b) 200 400 600 800 1000 1200 1400 1600 1800 2000

  • 1
  • 0.5

0.5 1 INTEGRAL NONLINEARITY vs. DIGITAL OUTPUT CODE DIGITAL OUTPUT CODE INL(LSB for 11b)

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SLIDE 50

SNDR vs. Sampling Frequency

50 10 20 30 40 50 60 70 20 40 60 80 100 SNDR (dB) Sampling Frequency (MHz)

SNDR vs Sampling Frequency

Variant 1 Variant 2

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SLIDE 51

Rail-to-Rail Output Swing

51 58 60 62

  • 5
  • 4
  • 3
  • 2
  • 1

SNDR (dB) Input Amplitude (dBFS)

Rail-to-rail output swing test

VDD = 1.2V Vrefp = 1.2V Vrefn = 0V fs = 4MHz

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SLIDE 52

Ring Amp Supply Sensitivity

52 50 52 54 56 58 60 62 64 1050 1150 1250 1350 1450 SNDR (dB) Supply Voltage (mV)

Ring Amplifier Supply Sensitivity

Vrefp = 1100mV

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SLIDE 53

Supply Current vs. Dead-zone

53 50.0 75.0 100.0 125.0

  • 300
  • 200
  • 100

100 200 300 400 Supply Current (uA) Deadzone (mV pk-pk differential)

Supply Current vs. Stage 1 Deadzone