A 12-bit low-power ADC for SKIROC Laurent ROYER, Samuel MANEN, Pascal GAY LPC Clermont-Ferrand L.Royer– Calice Meeting @ DESY – March. 2009
ADC requirements for Si-W Ecal channel n � Consumption: Consumption: C C � For ADC, arbitrary limited to 10% of the Shaper ADC SCA VFE power budget) 1 AMPLI. A A N � 2.5 µW/ch max. N A Charge Charge A A L L Shaper � Power pulsing needed pre-amplifier L O 10 -12 bits O G 10 T G filtered signal M O D E � I Resolution: M G Shaper O I � 12 bits (with a 2-gain shaping) � 12 bits (with a 2 gain shaping) R 100 100 pre-amplified signal pre amplified signal T T Y A L Discri. Shaper � Time of conversion: TRIGGER Fast � Time budget of 500 µs to convert all g µ data of all triggered channels channel n+1 SCA ADC 10 -12 bits � Compactness A/D A/D conv. DAQ DAQ IDLE MODE IDLE MODE A Analog electronics busy l l t i b 1ms (.5%) .5ms (.25%) .5ms (.25%) 198ms (99%) 2 L.Royer– Calice Meeting @ DESY – March. 2009
Cyclic ADC well-adapted for a one-ADC-per-channel architecture 64 channel V FE chip 64-channel V FE chip sh a p e r 1 analog m em ory analog m em ory sh a p e r 1 p re am p p re am p 12-bit A D C 12-bit A D C sh a p e r 1 0 sh a p e r 1 0 analog m em ory analog m em ory sh a p e r 1 analog m em ory analog m em ory sh a p e r 1 p ream p p re am p 12-bit A D C 12-bit A D C sh a p e r 1 0 sh a p e r 1 0 analog m em ory analog m em ory igital Data Bus sh a p e r 1 analog m em ory analog m em ory sh a p e r 1 p re am p p re am p 12-bit A D C 12-bit A D C sh a p e r 1 0 sh a p e r 1 0 analog m em ory analog m em ory .... . . .... .... .... Di 32 channels 32 channels sh a p e r 1 analog m em ory analog m em ory sh a p e r 1 p re am p p re am p 12-bit A D C 12-bit A D C sh a p e r 1 0 sh a p e r 1 0 analog m em ory analog m em ory D igital electronics With one-ADC-per-channel architecture: ☺ Short analog sensitive wires from memory to ADC ☺ A digital Data Bus far from sensitive analog signals ☺ A di it l D t B f f iti l i l Integrity of analog signals saved ☺ Only ADCs of triggered channels powered ON Power saved ☺ Conversions of channels done in parallel ☺ Conversions of channels done in parallel No "fast" ADC required No fast ADC required � Pedestal dispersion of ADC "added" to the dispersion of the analog part …. but calibrated 3 L.Royer– Calice Meeting @ DESY – March. 2009
The 12-bit cyclic ADC � Low cost technology: 0.35 µm CMOS Austriamicrosystems � Clock frequency: 1MHz � Resolution: 12 bits � Supply voltage : 3.5V � Power pulsing system implemented � Digital process of the bits (1.5 bit/stage algorithm) done with an external FPGA � 10 chips have been tested � Results in the Calice Internal Note CIN-14 � R lt i th C li I t l N t CIN 14 4 L.Royer– Calice Meeting @ DESY – March. 2009
Power pulsing measurement 1 µs for recovery time after swicth ON included Master current sources aste cu e t sou ces switched OFF 5 L.Royer– Calice Meeting @ DESY – March. 2009
Power pulsing measurement Variation of consumption vs Duty cycle of power pulsing 100 100 on ( in %) 90 80 zed in %) 70 Consumptio sumption (normaliz 60 50 40 Relative C 30 Cons 20 10 0 0 20 40 60 80 100 Duty cycle (% ON/(ON+OFF)) Duty cycle ( time ON / total time of one cycle in %) 6 L.Royer– Calice Meeting @ DESY – March. 2009
Instability Unstable amplifier Stable amplifier � The problem has been fixed � Common Mode FeedBack instability p y with process fluctuation � Chip submitted in March 09 to test the improvement 7 L.Royer– Calice Meeting @ DESY – March. 2009
Measurement of the Linearity INL<+/-1 LSB DNL<+/-1 LSB No missing code g 8 L.Royer– Calice Meeting @ DESY – March. 2009
Estimation of the Noise C d Code distribution (input 1V) di t ib ti (i t 1V) Standard deviation = 0.84 LSB (420µV) 9 L.Royer– Calice Meeting @ DESY – March. 2009
A Building Block for the next version Skiroc Clock generator 2 2 2 2 2 reset clock_amp clock_comp read Control signals Common Mode Common Mode to 4 Digital Vin 2 12-bit ADC Digital Output Differential Analog Input processing Interface DC voltages Power Supply Threshold C.M. Ref. Digital Analog +/-0.125V 1.5V +/-0.5V 3.0V 3.0V 2 2 DC voltages supply 10 L.Royer– Calice Meeting @ DESY – March. 2009
Summary � Measured performance in accordance with Si-W ECAL VFE requirements � Time conversion < 7µs � Consumption < 0.6µW per channel (power pulsing included) C ti 0 6 W h l � 2.5% of the power budget of one VFE channel � Linearity: DNL < +/1 LSB & INL < +/-1 LSB � Noise standard deviation < 0.8 LSB � Yield improved with the new design of the amplifier � A 12-bit cyclic ADC, dedicated to Si-W ECAL of ILC ready to be implemented in the next Skiroc chip. 11 L.Royer– Calice Meeting @ DESY – March. 2009
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