A 12-bit low-power ADC for SKIROC Laurent ROYER, Samuel MANEN, - - PowerPoint PPT Presentation

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A 12-bit low-power ADC for SKIROC Laurent ROYER, Samuel MANEN, - - PowerPoint PPT Presentation

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A 12-bit low-power ADC for SKIROC Laurent ROYER, Samuel MANEN, Pascal GAY LPC Clermont-Ferrand L.Royer Calice Meeting @ DESY March. 2009 ADC requirements for Si-W Ecal channel n Consumption: Consumption: C C For ADC,

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SLIDE 1

A 12-bit low-power ADC for SKIROC

Laurent ROYER, Samuel MANEN, Pascal GAY LPC Clermont-Ferrand

L.Royer– Calice Meeting @ DESY – March. 2009

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SLIDE 2

C

channel n

Consumption:

ADC requirements for Si-W Ecal

C

AMPLI.

1

Shaper Charge A N A SCA A N A L ADC

  • Consumption:

For ADC, arbitrary limited to 10% of the VFE power budget)

2.5 µW/ch max.

10 100

Shaper Shaper Charge pre-amplifier A L O G M E M O R L O G D I G I T T O 10 -12 bits

pre amplified signal filtered signal

Power pulsing needed

  • Resolution:

12 bits (with a 2 gain shaping)

100 Fast

Shaper Discri. Y T A L

TRIGGER

pre-amplified signal

12 bits (with a 2-gain shaping)

  • Time of conversion:

Time budget of 500 µs to convert all

SCA

channel n+1

ADC 10 -12 bits

g µ data of all triggered channels

  • Compactness

A l l t i b

A/D DAQ IDLE MODE

L.Royer– Calice Meeting @ DESY – March. 2009

2 Analog electronics busy 1ms (.5%)

A/D conv.

.5ms (.25%)

DAQ

.5ms (.25%)

IDLE MODE

198ms (99%)

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SLIDE 3

Cyclic ADC well-adapted for a

  • ne-ADC-per-channel architecture

64 channel V FE chip

p re am p sh a p e r 1 0 analog m em ory analog m em ory sh a p e r 1 12-bit A D C analog m em ory sh a p e r 1 p re am p sh a p e r 1 0 analog m em ory analog m em ory sh a p e r 1 12-bit A D C analog m em ory sh a p e r 1

64-channel V FE chip

p ream p sh a p e r 1 0 analog m em ory 12-bit A D C p re am p sh a p e r 1 0 analog m em ory analog m em ory sh a p e r 1 12-bit A D C

. .

p re am p sh a p e r 1 0 analog m em ory 12-bit A D C p re am p sh a p e r 1 0 analog m em ory analog m em ory sh a p e r 1 12-bit A D C

igital Data Bus

p re am p sh a p e r 1 0 analog m em ory analog m em ory sh a p e r 1 12-bit A D C

....

32 channels

....

p re am p sh a p e r 1 0 analog m em ory analog m em ory sh a p e r 1 12-bit A D C

....

32 channels

....

Di

☺ Short analog sensitive wires from memory to ADC ☺ A di it l D t

B f f iti l i l

With one-ADC-per-channel architecture:

D igital electronics

☺ A digital Data Bus far from sensitive analog signals ☺ Only ADCs of triggered channels powered ON ☺ Conversions of channels done in parallel

Integrity of analog signals saved Power saved No "fast" ADC required

L.Royer– Calice Meeting @ DESY – March. 2009

☺ Conversions of channels done in parallel Pedestal dispersion of ADC "added" to the dispersion of the analog part …. but calibrated

No fast ADC required

3

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SLIDE 4

The 12-bit cyclic ADC

Low cost technology: 0.35 µm CMOS Austriamicrosystems Clock frequency: 1MHz Resolution: 12 bits Supply voltage : 3.5V Power pulsing system implemented Digital process of the bits (1.5 bit/stage algorithm) done with an external FPGA 10 chips have been tested R lt i th C li I t l N t CIN 14 Results in the Calice Internal Note CIN-14

L.Royer– Calice Meeting @ DESY – March. 2009

4

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SLIDE 5

Power pulsing measurement

1 µs for recovery time after swicth ON included

Master current sources

L.Royer– Calice Meeting @ DESY – March. 2009

aste cu e t sou ces switched OFF

5

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SLIDE 6

Power pulsing measurement

100

Variation of consumption vs Duty cycle of power pulsing

70 80 90 100 zed in %)

  • n ( in %)

30 40 50 60 sumption (normaliz

Consumptio

10 20 20 40 60 80 100 Cons

Relative C

Duty cycle (% ON/(ON+OFF))

Duty cycle ( time ON / total time of one cycle in %)

L.Royer– Calice Meeting @ DESY – March. 2009

6

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SLIDE 7

Instability

Stable amplifier Unstable amplifier

The problem has been fixed Common Mode FeedBack instability p y with process fluctuation Chip submitted in March 09 to test the improvement

L.Royer– Calice Meeting @ DESY – March. 2009

7

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SLIDE 8

Measurement of the Linearity

DNL<+/-1 LSB No missing code INL<+/-1 LSB g

L.Royer– Calice Meeting @ DESY – March. 2009

8

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SLIDE 9

Estimation of the Noise

C d di t ib ti (i t 1V) Code distribution (input 1V)

L.Royer– Calice Meeting @ DESY – March. 2009

Standard deviation = 0.84 LSB (420µV)

9

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SLIDE 10

A Building Block for the next version Skiroc

2

Clock generator

Control signals clock_amp clock_comp read reset 2 2 2 2

Common Mode

2 Vin 4 Analog Input Digital Output

12-bit ADC

Digital processing Common Mode to Differential Interface

Power Supply Analog Digital 3.0V 3.0V DC voltages Threshold Ref. +/-0.125V +/-0.5V C.M. 1.5V 2 2

DC voltages supply

L.Royer– Calice Meeting @ DESY – March. 2009

10

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SLIDE 11

Summary

Measured performance in accordance with Si-W ECAL VFE requirements

Time conversion < 7µs C ti 0 6 W h l Consumption < 0.6µW per channel (power pulsing included) 2.5% of the power budget of one VFE channel Linearity: DNL < +/1 LSB & INL < +/-1 LSB Noise standard deviation < 0.8 LSB

Yield improved with the new design of the amplifier A 12-bit cyclic ADC, dedicated to Si-W ECAL of ILC ready to be implemented in the next Skiroc chip.

L.Royer– Calice Meeting @ DESY – March. 2009

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