Design of a Low-Power Potentiostatic Second-Order CT Delta-Sigma ADC - - PowerPoint PPT Presentation

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Design of a Low-Power Potentiostatic Second-Order CT Delta-Sigma ADC - - PowerPoint PPT Presentation

Oct 29, 2023 208 likes •510 views

Low-power potentiostat 2 nd Order CT ADC for ECS 1/26 Design of a Low-Power Potentiostatic Second-Order CT Delta-Sigma ADC for Electrochemical Sensors Joan Aymerich Gubern joan.aymerich@imb-cnm.csic.es Integrated Circuits and Systems

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SLIDE 1

Low-power potentiostat 2nd Order CT ADC for ECS

  • J. Aymerich Gubern

PRIME 2017

Design of a Low-Power Potentiostatic Second-Order CT Delta-Sigma ADC for Electrochemical Sensors

Joan Aymerich Gubern joan.aymerich@imb-cnm.csic.es

Integrated Circuits and Systems (ICAS) Instituto de Microelectrónica de Barcelona, IMB-CNM(CSIC) June 2017

1/26

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SLIDE 2

Low-power potentiostat 2nd Order CT ADC for ECS

  • J. Aymerich Gubern

PRIME 2017

Trillion-Sensor Vision

Sensors/year Year

5 6 % / y e a r 21%/year 222%/year

Electrochemical sensors are growing exponentially due to potential of miniaturization and mass production

2/26

Several organizations created visions for continued growth to trillion(s) sensors Applications in biosensors, quality control, ... Expected sensor production growth per year $15 trillion by 2022 www.tsensorssummit.org Monolithic or hybrid integration

  • nto CMOS platforms
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SLIDE 3

Low-power potentiostat 2nd Order CT ADC for ECS

  • J. Aymerich Gubern

PRIME 2017 3/26

1 Amperometric Electrochemical Sensors Conclusions 2 Potentiostatic Modulator architecture 3 4 5 Proposed architecture Design methodology and trade-offs

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SLIDE 4

Low-power potentiostat 2nd Order CT ADC for ECS

  • J. Aymerich Gubern

PRIME 2017 4/26

1 Amperometric Electrochemical Sensors Conclusions 2 Potentiostatic Modulator architecture 3 4 5 Proposed architecture Design methodology and trade-offs

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SLIDE 5

Low-power potentiostat 2nd Order CT ADC for ECS

  • J. Aymerich Gubern

PRIME 2017 5/26

Amperometric Electrochemical Sensors

Measurement independent of the R and C impedances. Three electrodes: Rct = charge-transfer resistance Cdl = double-layer capacitance Interaction with microorganisms Interaction with microorganisms Selectivity by functionalization Reduced speed and life time Potentiostatic and amperometric

  • perations

Electrochemical time constant:

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SLIDE 6

Low-power potentiostat 2nd Order CT ADC for ECS

  • J. Aymerich Gubern

PRIME 2017

Classic circuit implementation

A1 establishes the control loop to accomplish potentiostat operation & Requires multiples OpAmps + ADC A2 converts sensor current to voltage for digitization and readout Large area and power consumption Potentiostat Amperometry

6/26

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SLIDE 7

Low-power potentiostat 2nd Order CT ADC for ECS

  • J. Aymerich Gubern

PRIME 2017 7/26

2 Potentiostatic Modulator architecture 1 Amperometric Electrochemical Sensors Conclusions 3 4 5 Proposed architecture Design methodology and trade-offs

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SLIDE 8

Low-power potentiostat 2nd Order CT ADC for ECS

  • J. Aymerich Gubern

PRIME 2017

Behaviour similar to low-pass first-order single-bit CT A/D modulator Error current converted into voltage and shaped in frequency by the electrochemical sensor itself High oversampling ratios (OSR>100) can be easly obtained with kHz-range clock frequencies fS

8/26

Potentiostatic

Amperometric read-out through the modulation of output bit stream by chemical input

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SLIDE 9

Low-power potentiostat 2nd Order CT ADC for ECS

  • J. Aymerich Gubern

PRIME 2017

Behaviour similar to low-pass first-order single-bit CT A/D modulator Error current converted into voltage and shaped in frequency by the electrochemical sensor itself High oversampling ratios (OSR>100) can be easly obtained with kHz-range clock frequencies fS Monolithic CMOS integration Inexpensive 2.5 in-house CMOS technology (CNM25) developed by ICAS group at IMB-CNM(CSIC)

9/26

Electrochemical sensor Potentiostatic

Potentiostatic

Amperometric read-out through the modulation of output bit stream by chemical input

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SLIDE 10

Low-power potentiostat 2nd Order CT ADC for ECS

  • J. Aymerich Gubern

PRIME 2017

Typical tonal component of 1st order Typical tonal component of Quantization error and input signal correlation Potentiostat operation not well-defined Potentiostatic error influenced by the input signal

Electrochemical sensor

10/26

Quantizer

Potentiostatic

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SLIDE 11

Low-power potentiostat 2nd Order CT ADC for ECS

  • J. Aymerich Gubern

PRIME 2017 11/26

3 Proposed architecture 1 Amperometric Electrochemical Sensors Conclusions 2 Potentiostatic Modulator architecture 4 5 Design methodology and trade-offs

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SLIDE 12

Low-power potentiostat 2nd Order CT ADC for ECS

  • J. Aymerich Gubern

PRIME 2017

Higher resolution: 2nd order noise shaping Idle tones attenuation Potentiostatic operation well-defined New design trade-offs! Incremental work: Addition of electronic integration Stability compensation is required A zero must be added in the loop filter to compensate the phase shift

Proposed amperometric potentiostatic M

Electronic integrator forces

12/26

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SLIDE 13

Low-power potentiostat 2nd Order CT ADC for ECS

  • J. Aymerich Gubern

PRIME 2017

Stability compensation

Distributed FeedBack Topology

Loop Filter Zero frequency location

13/26

High frequency path

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SLIDE 14

Low-power potentiostat 2nd Order CT ADC for ECS

  • J. Aymerich Gubern

PRIME 2017

Stability compensation

Distributed FeedBack Topology

fZ depends on sensor time constant

8/15

Frequency [Hz] Loop filter gain [dB]

Loop Filter (s) fZ Leading to instability!!

14/26

Loop Filter Zero frequency location

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SLIDE 15

Low-power potentiostat 2nd Order CT ADC for ECS

  • J. Aymerich Gubern

PRIME 2017

Stability compensation

Distributed FeedBack Topology

0.025 0.02 0.015 0.01 0.005

  • 0.005
  • 0.01
  • 0.015
  • 0.02
  • 0.025
  • 0.2
  • 0.4
  • 0.6
  • 0.8
  • 1

0.2 0.4 0.6 0.8 1

DC Input [Full Scale]

Potentiostatic voltage strongly influenced by the sensor input signal

8/15

Frequency [Hz] Loop filter gain [dB]

Distributed feedback 1st Order

fZ depends on sensor time constant

Loop Filter Zero frequency location

fZ Leading to unstability!!

15/26

Loop Filter (s)

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SLIDE 16

Low-power potentiostat 2nd Order CT ADC for ECS

  • J. Aymerich Gubern

PRIME 2017

Stability compensation

Feed-Forward Topology

Loop Filter Zero frequency location

Variations in the sensor time constant do not compromise the stability of the system!

1 5

10

4

  • 3

10

  • 2

10

  • 1

10 10

2

10

5

10

3

10

1

Frequency [Hz] Loop gain [dB]

16/26

High frequency path

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SLIDE 17

Low-power potentiostat 2nd Order CT ADC for ECS

  • J. Aymerich Gubern

PRIME 2017

Stability compensation

Feed-Forward Topology Variations in the sensor time constant do not compromise the stability of the system!

0.025 0.02 0.015 0.01 0.005

  • 0.005
  • 0.01
  • 0.015
  • 0.02
  • 0.025
  • 0.2
  • 0.4
  • 0.6
  • 0.8
  • 1

0.2 0.4 0.6 0.8 1

DC Input [Full Scale]

Distributed feedback Feedforward 1st order

Electronic integrator forces its input to have DC zero component.

1 5

10

4

  • 3

10

  • 2

10

  • 1

10 10

2

10

5

10

3

10

1

Frequency [Hz] Loop gain [dB]

17/26

Loop Filter (s)

Loop Filter Zero frequency location

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SLIDE 18

Low-power potentiostat 2nd Order CT ADC for ECS

  • J. Aymerich Gubern

PRIME 2017 18/26

4 1 Amperometric Electrochemical Sensors Conclusions 2 Potentiostatic Modulator architecture 3 5 Proposed architecture Design methodology and trade-offs

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SLIDE 19

Low-power potentiostat 2nd Order CT ADC for ECS

  • J. Aymerich Gubern

PRIME 2017

Stability condition:

Real axis poles location / fs

0.2 0.4 0.6 0.8 1 1.2 1.4 1.6 1.8

  • 0.4
  • 0.2

0.2 0.4 0.6

(a)(b)(c) (a) (b) (c)

Root locus analysis: Closed-loop poles moves as quantizer gain changes

Small-Signal Stability Analysis

Linear model

Stability region as a function of fZ/fS

19/26 Linear model

Quantizer Gain DAC

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SLIDE 20

Low-power potentiostat 2nd Order CT ADC for ECS

  • J. Aymerich Gubern

PRIME 2017

Stability condition:

Linear model

Quantizer Gain DAC

Real axis poles location / fs

0.2 0.4 0.6 0.8 1 1.2 1.4 1.6 1.8

  • 0.4
  • 0.2

0.2 0.4 0.6

(a)(b)(c)

(a) (b) (c)

Small-Signal Stability Analysis

Linear model

Stability region as a function of fZ/fS

20/26

Less safety stability margin Better noise shaping Power Spectrum as function of zero location

Root locus analysis: Closed-loop poles moves as quantizer gain changes

(More 1st order behaviour)

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SLIDE 21

Low-power potentiostat 2nd Order CT ADC for ECS

  • J. Aymerich Gubern

PRIME 2017

Potentiostat Voltage Ripple

Feedback current DAC (IFS) charges/discharges Cdl TS is the only degree of freedom to minimize ripple (Cdl and IFS are fixed by the application) Voltage ripple may be required to be kept below certain minimum

21/26

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SLIDE 22

Low-power potentiostat 2nd Order CT ADC for ECS

  • J. Aymerich Gubern

PRIME 2017

SQNR vs input signal

22/26

Top-level simulation

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SLIDE 23

Low-power potentiostat 2nd Order CT ADC for ECS

  • J. Aymerich Gubern

PRIME 2017

Low-power circuit implementation

Electronic integrator: Gm1-C1 Feed-Forward path Latch comparator for 1-bit quantization

23/26

Feedback current DAC Power consumption mainly determined by current DAC FS, allowing chemical reaction take place D-type flip-flop for S/H Flexible and modular to be mapped into different CMOS technologies

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SLIDE 24

Low-power potentiostat 2nd Order CT ADC for ECS

  • J. Aymerich Gubern

PRIME 2017

Cyclic Voltammetry

Simulation Results

Performance simulation results Triangular waveform is applied to the Reference-electrode, while the sensor current is measured simultaneously. VerilogA model Power consumption mainly determined by current DAC FS Rest of circuit blocks Method for studying electrochemical reactions

Ferrocyanide Cyclic Voltammetry 24/26

CMOS technology

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SLIDE 25

Low-power potentiostat 2nd Order CT ADC for ECS

  • J. Aymerich Gubern

PRIME 2017 25/26

Conclusions 5 1 Amperometric Electrochemical Sensors 2 Potentiostatic Modulator architecture 3 4 Proposed architecture Design methodology and trade-offs

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SLIDE 26

Low-power potentiostat 2nd Order CT ADC for ECS

  • J. Aymerich Gubern

PRIME 2017

Conclusions

High resolution with kHz-range clock frequencies:

26/26

Compact architecture thanks to the electrode-electrolyte interface used as an integrator stage in the structure Minimalist analog circuits fully integrable in purely digital CMOS technologies Ultra low-power ( ) operation compared to sensor consumption

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SLIDE 27

Low-power potentiostat 2nd Order CT ADC for ECS

  • J. Aymerich Gubern

PRIME 2017

Conclusions

High resolution with kHz-range clock frequencies:

26/26

Compact architecture thanks to the electrode-electrolyte interface used as an integrator stage in the structure

Energy storage Electrochemical sensor <1mm2 ASIC: Potentiostat RF antennas Smart tags for food quality control Wireless contact lens for health monitoring

Minimalist analog circuits fully integrable in purely digital CMOS technologies

Future work

Ultra low-power ( ) operation compared to sensor consumption

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SLIDE 28

Low-power potentiostat 2nd Order CT ADC for ECS

  • J. Aymerich Gubern

PRIME 2017

Power Consumption Comparison

1/15 ECS Design Trade-offs Circuit Simulation Conclusions

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SLIDE 29

Low-power potentiostat 2nd Order CT ADC for ECS

  • J. Aymerich Gubern

PRIME 2017

Linear model

Quantizer Gain DAC Real axis poles location / fs

0.2 0.4 0.6 0.8 1 1.2 1.4 1.6 1.8

  • 0.4
  • 0.2

0.2 0.4 0.6 (a)(b)(c)(d)

From stable situation

Small-Signal Stability Analysis

Linear model

1/15 ECS Design Trade-offs Circuit Simulation Conclusions

Root Locus Stability region as a function of K Worst-case scenario when K is maximum

Root Locus

Real Axis (seconds

  • 1)

Imaginary Axis (seconds

  • 1)

Stability region as a function of fZ/fS

Sweep input: 0 to FS to find maximum quantizer gain Kmax (worst-case) Sweep fS/fZ and check if Kmax is within the stable region

Stability is ensured if: