Low Power Design Prof. Dr. J. Henkel CES - Chair for Embedded - PowerPoint PPT Presentation

Low Power Design Prof. Dr. J. Henkel CES - Chair for Embedded Systems KIT, Germany V. Thermal Aspects of Low Power Design – Part 1 Prof. Jörg Henkel, Low Power Design, SS2014 ces.itec.kit.edu

2 Why design for low power/energy? Portable Systems n Thermal Considerations n Notebooks, palm-tops, PDA, ä 10 o C increase in operating ä cellular phones, pagers, etc. temperature => component 32% of PC market, and growing l failure rate doubles Battery-driven - long battery life ä Packaging: ceramic vs . plastic ä crucial Cooling requirements ä System cost, weight limited by ä batteries Increasing levels of n 40W, 10 hrs @ 20-35 W- l integration / clock hr/pound = 7-20 pounds (Src: A. Raghunathan, NEC) frequencies make the Slow growth in battery l technology problem worse Must reduce energy drain LOW n 10cm 2 , 500 MHz => 315Watts ä from batteries POWER Reliability Issues n Environmental Concerns Electro-migration n ä EPA estimate: 80% of office IR drops on supply lines ä ä equipment electricity is used Inductive effects ä in computers Tied to peak/average n “Energy Star” program to ä power consumption recognize power efficient PCs Power management standard ä for desktops and laptops Drive towards “Green PC” n Prof. Jörg Henkel, Low Power Design, SS2014 ces.itec.kit.edu

3 (Src: F. Pollack, Intel) Prof. Jörg Henkel, Low Power Design, SS2014 ces.itec.kit.edu

4 Overview Why do we need thermal management?: motivation Thermal basics Part 1 “Dark Silicon” Reliability concerns Means to handle temperature 1: Activity Migration Cooling Methods Means to handle temperature 2: DVFS Task Scheduling Task mapping Multi-core architectures 3D architectures Thermal Management at CES Prof. Jörg Henkel, Low Power Design, SS2014 ces.itec.kit.edu

5 Basic definitions Heat is thermal energy (joules) Heat transfer (watt = joules/s) Q Heat flux is heat transfer rate through given surface area ● Specific thermal capacity c (J/cm 3. K) of Material c material determines amount of heating Silica 1.55 Cu 3.45 ∆ Q = ∆ H 2 0 4.17 c T Air 0.0012 Temperature: T Prof. Jörg Henkel, Low Power Design, SS2014 ces.itec.kit.edu

6 Methods of heat transfer Conduction Thermal conductivity k (W/(m . k)) is a material constant Material k Silica 1.5 Cu 401 H 2 0 0.6 Air 0.025 Radiation: heat emitted as electromagnetic waves due to temperature dependent kinetic motion of charged particles in matter Convection: transfer of energy through movement of fluids Prof. Jörg Henkel, Low Power Design, SS2014 ces.itec.kit.edu

7 Power in Relation to Temperature  Basic temperature equation: t • 1 1 • ∫ dT = + − + = − + T t ( ) T Q t ( ) P t dt ( ) C Q P 34 1 0 C dt 33 . t Temperature (°C) 0 32 where Q is the heat dissipation rate. 31 t t − − 30 = − − = + − h c T t ( ) T ( T T e ) T t ( ) T ( T T e ) 29 0 SS 0 0 0 A 28 Heating Cooling 27  T SS is the steady state temperature the system will 26 25 asymptotically reach with current power configuration 0 10 20 30 21:49,0 21:50,6 21:52,2 21:53,7 21:55,2 21:56,7 21:58,2 21:59,7 22:01,2 22:02,7 22:04,2 22:05,7 22:07,2 22:08,7 22:10,2 22:11,7 22:13,2 22:14,7 22:16,2 22:17,7 22:19,2 22:20,7 22:22,2 22:23,7 22:25,2 Time (s)  Ambient temperature T A is minimum reachable temperature Prof. Jörg Henkel, Low Power Design, SS2014 ces.itec.kit.edu

8 Heat Remains a Problem … “Circuit heat generation is the main limiting factor for scaling of device speed and switch circuit density” By Jeff Welser, Director SRC Nanoelectronics Research Initiative, IBM, Folgerung? Opening Keynote Address ICCAD 2007 MTTF [years] 10 9.06 K. Skadron et al., ICCAD 2004 9 8.34 7.73 8 7.24 6.85 7 6 5 0 5 10 15 20 25 Temp (Celsius) (Src: K. Skadron: Low-Power Design and Temperature Management; IEEE Micro, Vol. 27, No. 6, 2007) Prof. Jörg Henkel, Low Power Design, SS2014 ces.itec.kit.edu

Temperature in 3D Problem: vertical heat flow Only one layer directly interfaces with the heat sink Heat needs to dissipate through multiple layers The heat sink is located on top of the chip Hot cores distant to the heat sink dissipate their heat through other layers Silicon has a low thermal conductivity! 150 W/(m*K) (Silicon) 401 W/(m*K) (Copper)

Heat Remains a Problem … “Circuit heat generation is the main limiting factor for scaling of device speed and switch circuit density” By Jeff Welser, Director SRC Nanoelectronics Research Initiative, IBM, Folgerung? Opening Keynote Address ICCAD 2007 Classical scaling Limited scaling S 2 Device count S 2 Device count Device frequency S Device frequency S Device power (cap) 1/S Device power (cap) 1/S Device power (V dd ) 1/S 2 Device power ( V dd ) ~1 1 Power Density S 2 Power Density (Src: “Dennard Scaling”)

11 Power/Temperature Wall  The Dark Silicon Problem emerged due to the utilization wall as a result of  Memory wall  Parallelism wall  Power Wall => Chips cannot be driven with a power greater than their power budgets given as TDP (thermal design power)  Power dissipation, peak power, and power density are the ultimate limiting factors , thus determining the amount of Dark Silicon  Power is more expensive than area  Regardless of available parallelism, chip organization & topology, multicore scaling is power limited  @22 nm: Dark Silicon≈20% -50% J. Allred, S. Roy, K. Chakraborty, “Designing for Dark Silicon: A Methodological Perspective on Energy Efficient Systems”, in ISLPED, 2012  @8 nm: Dark Silicon > 50%-70%  H. Esmaeilzadeh, E. Blem, R. St. Amant, K. Sankaralingam, D. Burger, “Dark Dark Silicon is must be kept powered-OFF Silicon and the End of Multicore Scaling”, in International Symposium on Computer Architecture (ISCA), 2011 Prof. Jörg Henkel, Low Power Design, SS2014 ces.itec.kit.edu

12 Power/Temperature Wall: Trends Even if there is unlimited Parallelism, The Speedup is limited by the Power Constraint => There will be Scaling Limits when Dark Silicon Dark Silicon Dominates H. Esmaeilzadeh, E. Blem, R. St. Amant, K. Sankaralingam, D. Burger, “Dark Silicon and the End of Multicore Scaling”, in International Symposium on Computer Architecture (ISCA), 2011 Prof. Jörg Henkel, Low Power Design, SS2014 ces.itec.kit.edu 12

Power/Temperature Wall: 13 Is Multi-Core Scaling Promising? Assumption: Scaling Factor S=2 45nm 32nm 22nm 65nm 2 Cores 4 Core 8 Core 16 Core @ < 2GHz @ >= 2GHz @ > 2GHz @ >= 2GHz 8 Dark Cores Tradeoff 22nm between #Cores and 16 Core Frequency @ >= 4GHz 12 Dark Cores Prof. Jörg Henkel, Low Power Design, SS2014 ces.itec.kit.edu

14 Impact of High Temperature Higher temperatures result in a lower Mean Time To Failure (MTTF) A 10° C increase in operating temperature cuts product lifetimes in half [ http://www.nanowerk.com ] reduces the lifetime of chip Temperature increase Infant Useful Time Wearout Mortality Failure rate Time MTTF Curve Prof. Jörg Henkel, Low Power Design, SS2014 ces.itec.kit.edu

15 Temperature and Reliability Electromigration: aging effect due to transport of mass in metal interconnects directly linked to temperature Basic Mean time to failure modeled by Black ’ s Equation:   Q   − =   n kT MTTF Aj e MTTF decreases exponentially with temperature [wikipedia]  Goal: reduce peak temperatures Prof. Jörg Henkel, Low Power Design, SS2014 ces.itec.kit.edu

16 Thermal Gradients Due to: a) Low-frequency power change, b) Workload change, c) Power management Affects MTTF Temperature analysis of Virtex-5 FPGA 53 Scr: Amrouch, Ebi, Henkel Temperature [°c] 52 using infrared 51 thermal camera 50 49 showing peak 48 spatial thermal 47 46 gradients of 45 0.12°C/ μ m 44 43 resulting in an 1 24 47 70 93 116 139 162 185 208 231 254 277 300 323 increase of electromigration Time [sec] and accelerated Virtex-5 with two PowerPC CPUs aging Spatial gradients Temporal gradients  Goal: balance spatial/temporal gradients Prof. Jörg Henkel, Low Power Design, SS2014 ces.itec.kit.edu

17 Thermal Gradients Corresponding Thermal image spatial gradient map 30 16 mm 0 [°C/mm] 18mm peak spatial gradient of 32°C/mm Prof. Jörg Henkel, Low Power Design, SS2014 ces.itec.kit.edu

18 Example of Potential Thermal Cycling in FPGAs Scr: Amrouch, Ebi, Henkel Thermal Camera Virtex-5 FPGA Activity migration between two cores at the rate of 154 MCycle Temperature [°C] Core1 Core2 63 60 57 54 51 48 45 1 67 133 199 265 331 397 463 529 595 661 727 793 859 925 991 1057 1123 1189 1255 1321 1387 1453 1519 1585 1651 1717 1783 1849 Time [sec] Prof. Jörg Henkel, Low Power Design, SS2014 ces.itec.kit.edu