Unparalleled Power Performance Confidential Information 1 Broadest - - PowerPoint PPT Presentation

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Unparalleled Power Performance Confidential Information 1 Broadest - - PowerPoint PPT Presentation

Unparalleled Power Performance Confidential Information 1 Broadest Portfolio of Low Power Differentiated IP Unparalleled Power Performance Confidential Information 2 Corporate Background Focused on differentiated low power mixed-signal IP


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Broadest Portfolio of Low Power Differentiated IP

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Focused on differentiated low power mixed-signal IP – Founded in 1995, based in the Silicon Valley – Independent with no external funding World-class mixed signal CMOS engineering staff – Extensive experience in advanced SoC designs – IP in billions of silicon from 0.25µm to 5nm FF Premier IP partner from architecture to silicon – Customer-centric business engagement – Engineering-centric support Global customer base: 50% US, 50% international – 500+ Customers in 70+ Processes Heritage Track Record Core Values Client Base

Corporate Background

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Merchant Fabs Process Names, (Red in Production, Black pre-production)

CL025, CL018G, CL018LV, CL018IMG, CL015G, CL015LV, CL013G, CL013LV CL013LVOD, CL011LV, CL011G, CLN90G, CLN90GT, CLN90LP, CLN80GC, CLN65LP, CLN65GP, CLN55GP, CLN40G, CLN40LP, CLN28HP, CLN28HPL, CLN28HPM, CLN28HPC, CLN28HPC+, CLN22ULL, CLN20SOC, 16FFT, 16FF+, 16FFC, 12FFC, N7, N7+, N6, N5, N5P 45LP, 32LP, 28LP, 28FDSOI, 14LPP, 8LPP, 7LPP, 5LPE 0.13u, CH90G, CH90LP, CH65G, CH65LP, CH65LPE, CH45LP, 40LP, 32LP, 28SLP, 22FDX, 14LPP, 12LP, 12LP+ L250, L180 HS, L150 HS, L130E HS, L130 SP, L130 LL, L90SP, L90G, 65SP, 65LL, 40LP, 28HPL, 22ULL

IDM Fabs Low Cost Fabs

70+ Processes and 700+ IP Products Delivered

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§ Industry’s broadest and most pervasive clocking IPs § Wide-range programmable PLL § High-end Audio / Video Class PLL – FracN/SSCG PLL § Ultra low jitter sub-picosecond LC PLL § PCIe Clock PHY IP § High performance C2C PLL § Ultra low power sub-micro watt IOT class PLL § High reliability radiation tolerant PLL

Clocking IP Volume Leader

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Portfolio of Low Power PLL in Bulk, FDSOI and FinFet’s

§ Low Power Wide Range PLL

– Wide input and output frequencies – Low and low power – Wide operating voltage and temperature – Automotive Grade 1 in 22DX

§ Frac-N/SSCG PLL

– Fine precision 1 part per billion – Wide input and output frequencies – Low area: and low power

§ Chip-Chip PLL

– Ring OSC based VCO offers a wide range of output frequency – Integrated LDO to reduce deterministic jitter – Low Area – CML output option

Low Power Integer PLL Low Area Chip 2Chip PLL Frac-N/SSCG PLL

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Integrated Low Power SoC Sensors in FDSOI and FinFets

§ On Die PVT Sensor

– Fully integrated in single macro – Low power and small form factor – High accuracy – Automotive grade in 22 FDX

§ Integrated POR

– Detects power stability of both core and IO – Easy to use and configure – Brown out prevention – OCD

§ Power Supply Glitch Detector

– Independent programming of glitch levels – Cascade by abutment for multiple monitoring – Integrated voltage reference

Integrated PVT Sensor POR Macro with OCD Power Supply Glitch Detectors

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§ Differential clock transmitter and receiver § PCI-Express - HCSL clock drivers § C2C IO’s § Low noise and low power crystal oscillators § Lowest Power Crystal-less OSC pads for IoT § FPGA class multi-programmable IO § Voltage tolerant IO buffers § DDR IO’s

Differentiated IO for High Performance & Low Power/Cost IoT Markets

7nm Differential IO TX/RX 7nm CML Pads

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§ Multi-rate, multi-protocol SERDES

– Lowest power & latency – Smallest area – Programmable for numerous channel environments

§ And enabling many SOC applications

FPGA Consumer Cables Mobile Computing DataCenters & Communications Flat Panel Display Wearables

Analog Bits Low-Power, Multi-Protocol SERDES

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Lowest Power PCIe3/SATA3 SERDES

Production Proven in TSMC 28HPC+, Samsung 28LPP/28FDSOI

28nm Bulk SERDES Layout

Process Area

(sq. mm)

PCIe Power

(worst case PVT)

Dynamic Power

(mW/Gbps)

Leakage Power

(MicroWatts)

28LP Bulk 0.100 54.93 6.9 46.6 28 FD SOI 0.100 53 6.7 30.5

28nm FDSOI SERDES Layout

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Why Analog Bits

Differentiated IP with broadest portfolio focused with best in class PPA Excellent Reputation for best-in-class mixed signal designs in the Silicon Valley Global Customer Base from 0.25µm to 5nm FinFET Volume Business Friendly no royalty model