DUNE COLD ADC UPDATE #2 Carl Grace, LBNL May 16, 2018 Advancing - - PowerPoint PPT Presentation

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DUNE COLD ADC UPDATE #2

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Carl Grace, LBNL

May 16, 2018

Carl Grace

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Reminder from last time

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Carl Grace

• Cold ADC is a 16-channel, 12-bit, 2 MS/s Digitizer ASIC to

replace the current ADC ASIC

• Designed by joint team from LBNL, FNAL, and BNL
• Key design goal: first time success
• Cold ADC uses a conservative, industry-standard design

with digital self-calibration

• Besides functionality and reliability, design goal is low-

noise operation

• Design contains significant features for risk mitigation and
• bservability

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Outline

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Carl Grace

• Design Partitioning
• Current Status
• BJT Measurements and Backup Reference
• A Note on Risk Mitigation (Functional Verification)
• New Simulated Results

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Carl Grace

Design Responsibilities

BNL LBNL FNAL

S/H Correction Logic Data Formatter IN0 IN7 I2C DIG_OUTA(P/N) DIG_OUTB(P/N) I2C_(SCL,SDA, SDO) CLK_64MHZ(P/N) S/H 12-bit 16 MS/s Pipelined ADC DIG_FRAME(P/N) DIG_CLKOUT(P/N) BJT-based Reference Generation

Cold ADC

8-1 MUX DIG_OUTC(P/N) DIG_OUTD(P/N) LVDS I/O BUFFER BUFFER S/H Correction Logic IN8 IN15 S/H 12-bit 16 MS/s Pipelined ADC 8-1 MUX BUFFER BUFFER UART MISO/MOSI Configuration and Debug Interface IMONITOR VMONITOR DIG_OUTE(P/N) DIG_OUTF(P/N) DIG_OUTG(P/N) DIG_OUTH(P/N) CLK_16MHZ(P/N) CLK_2MHZ(P/N) I2C_ADD SSO_(FRAME, DATA[1:0], CLK) VREF(P,N,CMI,CMO), BGR VDD/VSS domains LVDS_REF Calibration Engine Calibration Engine 30 16 16 30 16 16 BUFFER + S2D CMOS-based Reference Generation ADC Reference Buffers

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Outline

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Carl Grace

• Design Partitioning
• Current Status
• BJT Measurements and Backup Reference
• A Note on Risk Mitigation (Functional Verification)
• New Simulated Results

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Current Status

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Carl Grace

• 1st Pass of chip schematics complete
• Currently undergoing deep review process, where each

team reviews circuits of other teams to improve quality

• Setting up Analog/Digital co-simulations
• A few blocks have been laid out to exercise design flow;

comprehensive layout design to begin after deep review

• Cold ADC is on-track for summer submission

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Outline

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Carl Grace

• Design Partitioning
• Current Status
• BJT Measurements and Backup Reference
• A Note on Risk Mitigation (Functional Verification)
• New Simulated Results

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BJT Measurements

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Carl Grace

• Bipolar transistors (BJTs) are critical for accurate

reference voltage generation

• Unfortunately, the cold models available for LAr

temperature do not include BJTs

• As luck would have it, LBNL developed a chip in 2011 in

the same process (65nm) at the same foundry, that happened to include some BJT test structures

• Both BNL and LBNL measured some of these devices at

cold and correlated their results to inform the design of a BJT-based voltage reference

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BJT Bonding

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Carl Grace

Each test device is a 5x5 array of standard BJTs

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BJT Measurements (77 K)

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Carl Grace 1.00E-13 1.00E-11 1.00E-09 1.00E-07 1.00E-05 1.00E-03 1.00E-01

0.2 0.4 0.6 0.8 1 1.2

IE(A) VE(V)

IE X VE WITH VB=VC=0, 77K LBNL BNL

Measurements mostly agree, but simulation more than an order-of- magnitude off! Can use measured values to build a voltage reference, but we only measured a single device from one fabrication run done 7 years ago… Design CMOS reference for backup

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CMOS Reference (current ref)

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Carl Grace

CMOS reference

INT MP2 MP1 VDDA

Startup

MN1 MP3 EXT RBIAS RBIAS_EXT MN2 MP4 RDROP RPULLUP MN3 MN4 MN5 MP5 IREF KICKSTART_B TRIM<2:0> MP6-8

Adjust reference current using trim and monitor output

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CMOS Reference (simulation)

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Carl Grace

About 5% shift in bias current across temperature. Not amazing but good enough for ADC.

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Outline

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Carl Grace

• Design Partitioning
• Current Status
• BJT Measurements and Backup Reference
• A Note on Risk Mitigation (Functional Verification)
• New Simulated Results

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Design Risk Mitigation

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BLOCK WORK-AROUND Buffer Bypass (directly connect LARASIC to ADC) ADC References Bypass (use external references) Bandgap Reference Select or bypass (use CMOS-based reference, external BGR, or external references) Bias Currents Highly adjustable to improve settling or reduce power at cold (for instance) Calibration Algorithm Calibrate off-line and load gain estimates into register file Correction Logic Use uncalibrated (traditional) ADC output Digital Interface to colData Route ADC data through SSO (can still evaluate ADC performance) Configuration Interface Read and Write with either I2C or UART ADC Gain Boosting Include gain booster kill switch

DUNE Cold ADC

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Design Risk Mitigation

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Carl Grace

• During the drafting of the DUNE Technical Proposal, Gary

Varner made the astute observation that while there are myriad benefits of high ASIC configurability, designing in so many knobs has its own risks and should be

• acknowledged. He is quite right.
• Through the use of a design methodology known as

Functional Verification, I claim that the unknown risks of device variability at cold temperature can be converted to the risk of botched configurability, and that second risk can be retired.

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Section 1: Berkeley Lab Mission

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• Exhaustive regression testing
• Check every mode and every setting (still possible in analog)
• Automate pass/fail tests (create self-checking testbenches)
• Model-based Verification
• Replaces transistor-level circuit with model
• Dramatically accelerates simulation
• Moves verification early into design cycle (improves top-down

design)

• Simplifies re-use of analog blocks
• Full-chip verification
• Use common environment to verify functionality of complex

mixed-signal loops such as gain control, frequency synthesis, or calibration

Model-based functional verification

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Presenter Name

12 ADC channels Biasing PLL Synthesized Logic 12 ADC channels 3 Serial TXs 3 Serial TXs

11.9 mm 5.4 mm

Reference Gen

Example of functional verification

HIPSTER (High-Speed Image Preprocessor Targeted for Electron Readout - 2015)

HIPSTER contained 549 configuration bits (PLL/EQ settings, ADC biasing, power downs, etc)

(Cold ADC has 381 configuration bits)

Using Functional Verification HIPSTER had zero configuration bit errors on first silicon

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Outline

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Carl Grace

• Design Partitioning
• Current Status
• BJT Measurements and Backup Reference
• A Note on Risk Mitigation (Functional Verification)
• New Simulated Results

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ADC Simulation (schematic)

16-bit ideal DAC readback 13 kHz full-scale sine input

Uncalibrated output

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Presenter Name

ADC Comparator Simulation

Room temperature Monte Carlo (400 runs) (spec. 62.5 mV-rms)

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Presenter Name

Backup Slides

BACKUP

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Reference Buffers

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• Reference Buffers drive ADC references
• Need to settle to better than about 0.25 LSB between

samples (define settling time as 1/3 clock period @ 20 MS/s for margin)

• Need Low Noise
• Noise in reference directly couples to input of ADC

Carl Grace

𝑊

𝑗𝑜

𝑊

𝑠𝑓𝑔

= −1 + 𝐸(𝑗) 2𝑗−1

𝑂 𝑗=1 ideal Pipelined ADC

transfer function

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Reference Buffers (cont.)

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Two Basic Approaches:

• 1. Slow, but don’t budge! Need a heavy capacitance
• 2. Fast so you can settle before next kick

Carl Grace

Vref_internal Vref_external Lbondwire Cd_ext Cd_local Cd_int Rtrace Vref_internal Vref Gen Cd_local Fast Buffer

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Reference Buffers (cont.)

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Approach 1 (low speed)

• We need Cd_ext to be large enough that switching ADC

capacitors doesn’t change Vref more than 0.25 LSB

• ΔQ = CADCVMAX = 8 pF *1.5 V = 12 pC
• Allowed ΔV = LSB/4 = 3.0/214 = 183 µV
• Cd_ext = ΔQ/ΔV = 12 pC / 183 µV = 66 nF (off-chip needed)
• Need to be mindful of capacitor speed and series

inductance + resistance

Carl Grace

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Reference Buffers (cont.)

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Approach 2 (high speed)

• Assuming linear settling, the output voltage of buffer will be:
• 𝑊 𝑢 = 1 − 𝑓−𝑢

τ where t is time and τ is the time constant.

• The maximum excursion is Vref/2. So, solving for t:
• 𝑢 = −ln

1 2∗2𝑂 = 9 τ for 12-bit settling.

• Since τ = RC, the settling spec. is 17 ns, and C = 8 pF, we

have: R = 17 ns / (9 * 8 pf) = 236 Ω. (Closed-loop Rout)

• Also, Δi = ΔQ/Δt = 12 pC / 17 ns = 700 µA

Carl Grace

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Reference Buffers (cont.)

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Approach 2 (cont)

• Buffer must supply significant current and have low output-

resistance  high gain.

• Buffer must also drive threshold-gen resistors  standing

current

• Solution  class AB opamp
• We choose Approach 2 so we don’t need large off-chip

capacitors

Carl Grace

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Reference Buffers (cont.)

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• To reduce power, use class AB “Monticelli” biasing

Carl Grace

D.M. Monticelli, “A Quad CMOS Single-Supply Op Amp with Rail-to-Rail Output Swing,” IEEE Journal of Solid-State Circuits, vol. SC-21, pp. 1026-1034, Dec. 1986

VOUT VIN MPCS MNCS VY Level-shift VX

VOUT VX VP VN MPB MPCS MNB MNCS VY IB IB Iin MN1 MN2 MP1 MP2 2*K1*IB 2*K1*IB IQ VDDA VSSA

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Reference Buffers (cont.)

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Carl Grace

PMOS input version (for low-voltage references)

MP8 MP7 MP4 VB4 VDDA VSSA MP3 MP2 VIP VIN MP1 MN2 VOUT MP6 MP5 VB3 MP9 VP VN 4 pF VB2 MP10 MN1 MN3 MN4 MN6 MN7 125 µA 125 µA 400 µA 400 µA 4 pF VB1 525 µA 525 µA 500 µA

3.49 mW nominal

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Reference Buffers (cont.)

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Carl Grace

NMOS input version (for high-voltage references)

MP2 MP1 VDDA VSSA MN6 VOUT MP4 MP3 VB3 MP5 VP VN VB2 MP6 MN5 MN3 MN4 MN10 MN7 250 µA 250 µA 4 pF MN2 MN1 VB1 VIP VIP VIN MN8 MN9 VB4 100 µA 100 µA 150 µA 150 µA 500 µA 4 pF

2.25 mW nominal

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Reference Buffers (cont.)

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Carl Grace

Bias Circuit. High currents for low noise.

VDDA VB<3> VB<2> MPTRI MPDIODE MPBIAS MPC MNTRI MNDIODE MNBIAS1 MNC MNBIAS2 MNBIAS3 MNCASC1 MNCASC2 VSSA IBIAS_IN VB<4> VB<1> MNINA MNINB MPINA MPINB MPINC 250 µA 250 µA 250 µA 250 µA 250 µA 250 µA MNVP1 MNVN1 MNVP2 MNVN2 250 µA 250 µA VN VP MPVP1 MPVP2 MPVN1 MPVP3 MNVN3

4.5 mW nominal

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Reference Buffers (cont.)

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Carl Grace

10 Ω resistors help settling for switched capacitor load

Vrefp_internal Vrefp

10 Ω

Vrefn_internal Vrefn

10 Ω

Vcmi_internal Vcmi

10 Ω

Rthresh Vcmo_internal Vcmo

10 Ω

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Reference Buffers (simulation)

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Carl Grace

Unloaded AC analysis for PMOS-input ref buffer DC Gain = 108 dB GBW = 61.6 MHz PM = 70.5 degrees Rout_ol = 50 kΩ Rout_cl = 0.2 Ω

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Reference Buffers (simulation)

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Carl Grace

Unloaded AC analysis for NMOS-input ref buffer DC Gain = 134 dB GBW = 59.5 MHz PM = 80 degrees Rout_ol = 70 kΩ Rout_cl = 0.1 Ω

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Reference Buffers (simulation)

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Carl Grace

Differential noise of VREFP – VREFN (including idealized resistive load) at room temperature (23 C) Cold specification is 50 µV-rms. AC simulation does not include switched-capacitor filtering effects Output noise density RMS output noise = 125.5 µV

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Reference Buffers (simulation)

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Carl Grace

Differential noise of VREFP – VREFN (including idealized resistive load) at LN2 temperature (-200 C) Cold specification is 50 µV-rms. AC simulation does not include switched-capacitor filtering effects Output noise density RMS output noise = 64.5 µV

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Reference Buffers (simulation)

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Carl Grace

Reference settling VREFP – VREFN at room temperature (23 C) including ADC load VREFP VREFN VREFD PHI1 PHI2

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Reference Buffers (simulation)

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Carl Grace

Reference settling VREFP – VREFN at LN2 temperature (-200 C) including ADC load VREFP VREFN VREFD PHI1 PHI2

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Reference Buffers (simulation)

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Carl Grace

100-run transient noise simulation (including ADC load). Peak-to-peak noise at sampling edge ~ 60 µV-rms VREFD PHI2P

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Reference Buffers (simulation)

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Carl Grace

Scatter-plot of sampled reference values for 100-run transient noise simulation (including ADC load). Standard deviation ~ 15.9 µV (well below specification)

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R-2R DAC for use with CMOS Ref

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Carl Grace

Does not depend on bandgap voltage (tradeoff is VDDA dependency)

R 2R R D0 D0 R

VREF

2R R D1 D1

VREF

2R R D7 D7

VREF CFILTER

Vout

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R-2R DAC (cont)

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Carl Grace

Resistor Matching: for 8-b DAC, resistors should match to (1/28) * 100% = 0.39% From Monte Carlo simulation, two 20 µm2 devices match to 0.19%. To reduce standing current (while providing adequate noise performance, R = 20 kΩ. Choose 40 µm2 for unit device (allowing for reduced matching at cold due to partial dopant freeze-out) Choose Cfilter = 10 pF for bandwidth limiting

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R-2R DAC (RT simulation)

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Carl Grace

Reference noise dominated by buffers Output noise density RMS output noise = 10.2 µV

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Section 1: Berkeley Lab Mission

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Superset of Verilog and Verilog-A

• Contains event-driven (digital) kernel
• Also contains continuous (analog) kernel
• Verilog, Verilog-A and Verilog-AMS models can be freely mixed

Verilog-AMS Verilog Verilog-A

Verilog-AMS

Mentor ADvanced-MS has single kernel for improved performance

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Verilog-AMS model Transistor-Level schematic Testbench Apply same self-checking testbench to model and schematic to validate model

Model Verification

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Mixed-Signal Verification

• Most functional errors are very simple:
• Inverted signals (e.g. enable or power-down controls)
• Corrupt logic (e.g. decoding of gain settings may be incorrect)
• Flipped busses (e.g. different blocks interpret same bus in different

ways)

• Unaccounted for dependencies (e.g. control register for LDO that is

powered by that LDO)

• Errors in control logic (e.g. blocks may not power down or power up

when required)

• Often due to miscommunication between engineers

“Simple” functional errors can render a chip inoperable and untestable (e.g. ADC that doesn’t power up)

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Section 1: Berkeley Lab Mission

SUBTITLE HERE IF NECESSARY

• Exhaustive regression testing
• Traceability to transistor level
• Blocks are verified hierarchically
• Verification of both models and circuits
• Models are pin-accurate
• Testbenches verify behavior of models
• Methodology assures models are consistent with circuits
• Also encourages and enables to-down design
• Develop models before schematics
• Model at highest level of abstraction possible
• Take care to capture functionality, not structure
• As simple as possible, but no simpler
• makes models faster, easier, and more maintainable

Analog verification methodology

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