������� �� �� ������ ����c�����c�����c�� �����������c�������c����� �������������� ������!� CMP annual users meeting, 18 January 2007, PARIS
����������"� ������� �� �� ������ • High density • Low power • More system Integration • More Process Features AMS 0.8µ AMS 0.6µ AMS 0.35µ ST 0.25µ ST 0.18µ ST 0.12µ ST 90nm ST 65nm 1.2k gates/mm 2 3k gates/mm 2 18k gates/mm 2 35k gates/mm 2 80k gates/mm 2 180k gates/mm 2 400k gates/mm 2 800k gates/mm 2 2006 at CMP 1994 at CMP CMP annual users meeting, 18 January 2007, PARIS
���c����#��$��� ������� �� �� ������ ������������������������� 3,5 3 Industry (SIA where available) Size, microns 2,5 CMP 2 1,5 1 0,5 0 Year 84 86 88 90 92 94 96 98 00 02 04 06 08 10 CMP annual users meeting, 18 January 2007, PARIS
%��!�� ���c�������� ����c�����c�����c� %��!�� %��!�� %��!�� ����c�����c�����c� ����c�����c�����c� ����c�����c�����c� ������� �� �� ������ ����c�����c�����c�� ����c�����c�����c�� ����c�����c�����c�� ����c�����c�����c�� ��!����&��� ��!����&���' ��!����&��� ��!����&��� ' ' ' %��!�� %��!�� %��!�� %��!�� CMP annual users meeting, 18 January 2007, PARIS
%��!������c��� %��!��� %��!��� %��!��� ���c��� �������� ���c��� ���c��� �������� �������� �������� ������� �� �� ������ � 0.12µ mixed A/D CMOS SLP/6LM (triple Well) � Gate length (0.13 µm drawn, 0.11 µm effective). � 6 Cu metal layers. (Up to 8 metal layers in option) � Low k inter-level dielectric � Power supply: 1.2 V � Multiple Vt transistor offering � (Ultra low leakage, low leakage, High speed) � Threshold voltages (for 3 families above) : � VTN = 570/500/380 mV, VTP = 590/480/390 mV � Isat (for 3 families above) : � TN @ 1.2 V : 410/535/680 uA/um; TP @ 1.2 V : 170/240/320 uA/um CMP annual users meeting, 18 January 2007, PARIS
%��!������c��� %��!������c��� %��!������c��� %��!������c��� ������� �� �� ������ �&��' ��(�$�)*����!���+�*�+�������$�c�$��,��������-.������ ~ 140 centers received design rules, design-kits • 4 runs + 1 special, organized in 2006 • 62 circuits (45 from France + 17 abroad) In 2005 60 circuits (13 from France + 47 abroad) • 2500 Euro/mm 2 6 levels Cu Metal (Cross Section View) Courtesy STMicroelectronics (25 samples for which 5 are packaged) ��� �� ��� �� ��������������� ��� �� ��� ��� �� ��� �� ��� �� ��� �� �� � � ���� ���� ���� ���� ���� ���� ���� ���� CMP annual users meeting, 18 January 2007, PARIS
��!���� ���c�������� ����c�����c�����c� ��!���� ��!���� ��!���� ����c�����c�����c� ����c�����c�����c� ����c�����c�����c� ������� �� �� ������ ����c�����c�����c�� ����c�����c�����c�� ����c�����c�����c�� ����c�����c�����c�� �������!�� �������!�� �������!�� �������!�� ��!���� ��!���� ��!���� ��!���� CMP annual users meeting, 18 January 2007, PARIS
��!�������!����������c������������ ��!�������!����������c������������ ��!�������!����������c������������ ��!�������!����������c������������ ������� �� �� ������ • 65nm poly length (90nm drawn) • Dual Vt MOS transistors • Dual gate oxide • Dedicated process flavors for high performance or low power • Dual-damascene copper for interconnect. • 7 metal layers for interconnection • 0.28um metallization pitch. • Analog / RF capabilities. • Fully compatible with e-DRAM • Various power supplies supported : 3.3V, 2.5V, 1.8V, 1.2V, 1V • Dual standard cell libraries (speed / density) (430 kgates/mm2 / 350 kgates/mm2). • Total of > 1000 core cells • Gate delay of 11ps (standard Vt) • Embedded memories SRAM / ROM CMP annual users meeting, 18 January 2007, PARIS
��!��������c��� ��!����� ���c��� ��!����� ��!����� ���c��� ���c��� ������� �� �� ������ 90nm mixed A/D CMOS 7LM introduced by CMP in Q3 2004 ~ 120 customers received design rules, design-kits • 4 MPW runs + 1 Taxi run, organized in 2006 • 4 MPW runs scheduled in 2007 5000 Euro/mm 2 • (25 samples for which 5 are packaged) CMP annual users meeting, 18 January 2007, PARIS
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