Hybrid CLS-Opamp/ZCBC Pipelined ADC Using a 300mV Output Swing - - PowerPoint PPT Presentation

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Hybrid CLS-Opamp/ZCBC Pipelined ADC Using a 300mV Output Swing - - PowerPoint PPT Presentation

Aug 10, 2023 168 likes •716 views

A 1.4V Signal Swing Hybrid CLS-Opamp/ZCBC Pipelined ADC Using a 300mV Output Swing Opamp Benjamin Hershberg Skyler Weaver Un-Ku Moon Oregon State University, Corvallis, OR Preview 1. Background Correlated Level Shifting

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SLIDE 1

A 1.4V Signal Swing Hybrid CLS-Opamp/ZCBC Pipelined ADC Using a 300mV Output Swing Opamp

Benjamin Hershberg Skyler Weaver Un-Ku Moon Oregon State University, Corvallis, OR

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SLIDE 2

Preview

  • 1. Background
  • Correlated Level Shifting
  • Zero-Crossing Based Circuits
  • 2. Hybrid CLS-Opamp/ZCBC Structure
  • 3. Dynamic Zero-Crossing Detector
  • 4. Measurement Results
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SLIDE 3

Correlated Level Shifting (CLS)

  • Finite opamp gain error becomes 1/A2
  • Opamp output tied to different nodes in Φ1 and Φ2

Gregoire, ISSCC 2008

ФS ФA Ф1 Ф2 CCLS Vo ФS ФA Ф1 Vi ФA Ф2 VCMI VCMO ФS Ф1 (+/-Vr,0)

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SLIDE 4

CLS – Basic Operation

Ф1 :

  • opamp charges output

directly

  • processes full signal

Opamp Design Requirements Ф1 Ф2 Output Swing Large Small Slew Rate Large Small CCLS Vo ФS ФA Ф1 Vi ФA Ф2 VCMI VCMO ФS Ф1 (+/-Vr,0)

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SLIDE 5

CLS – Basic Operation

Ф2 :

  • opamp is level shifted to

mid-rail

  • processes error only

Opamp Design Requirements Ф1 Ф2 Output Swing Large Small Slew Rate Large Small CCLS Vo ФS ФA Ф1 Vi ФA Ф2 VCMI VCMO ФS Ф1 (+/-Vr,0)

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SLIDE 6

Observation

  • Use separate charging devices for Ф1 and Ф2
  • Optimized design for each phase
  • Increase overall accuracy & efficiency
  • For this test chip:
  • Ф1: Zero-crossing based

circuit (ZCBC)

  • Ф2: Double-cascoded

telescopic opamp

Opamp Design Requirements Ф1 Ф2 Output Swing Large Small Slew Rate Large Small

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SLIDE 7

Ф1: Zero-crossing based circuit

VX

  • vershoot

VCM ФPC ФPC Vx VCM VCM VCM VSS ZCD Isrc

Sepke, ISSCC 2006

Slewing efficiency Easy to turn off during Ф2 No forced feedback Linearity and reliability challenges

Charges output until input virtual ground condition is detected

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SLIDE 8

Ф1: Zero-crossing based circuit

VX

  • vershoot

VCM ФPC ФPC Vx VCM VCM VCM VSS ZCD Isrc

Sepke, ISSCC 2006

Slewing efficiency Easy to turn off during Ф2 No forced feedback Linearity and reliability challenges

Charges output until input virtual ground condition is detected

Ф1 : Fast, coarse charging Φ2 : High accuracy feedback

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SLIDE 9

Ф2: Telescopic Opamp

High Gain High Speed Low Power Low Swing Low Slew

Vbn4 Vbn3 Vbp2 Vbp3 Vbn1

Vi+ Vi- Vo+ Vo-

Vctrl

VDD VSS

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SLIDE 10

Ф2: Telescopic Opamp

35dB (AФ1) + 75dB (AФ2) 110 dB High Gain High Speed Low Power Low Swing Low Slew Effective Gain

Vbn4 Vbn3 Vbp2 Vbp3 Vbn1

Vi+ Vi- Vo+ Vo-

Vctrl

VDD VSS

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SLIDE 11

Hybrid CLS-Opamp/ZCBC

Vo+ Vo-

SPC (ФPC) VSS VDD VSS VDD VCM

+Vref Vcm

  • Vref

ФS ФS ФS ФS ФS ФS ФA ФA

Vi+ Vi-

ФA ФA Vi+(n+1) Vi-(n+1) SPC (ФPC) IN IP

Vx+ Vx-

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SLIDE 12

Hybrid CLS-Opamp/ZCBC

Vo+ Vo-

SPC (ФPC) VSS VDD VSS VDD VCM

+Vref Vcm

  • Vref

ФS ФS ФS ФS ФS ФS ФA ФA

Vi+ Vi-

ФA ФA Vi+(n+1) Vi-(n+1) DC SPC (ФPC) IN IP

Vx+ Vx-

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SLIDE 13

Hybrid CLS-Opamp/ZCBC

CCLS CCLS

Vo+ Vo-

SPC (ФPC) VSS VDD VSS VDD VCM VCM

+Vref Vcm

  • Vref

ФS ФS ФS ФS ФS ФS ФA ФA SOP SOP

Vi+ Vi-

ФA ФA Vi+(n+1) Vi-(n+1) DC SPC (ФPC) IN IP

Vx+ Vx-

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SLIDE 14

Hybrid CLS-Opamp/ZCBC

CCLS CCLS

Vo+ Vo-

SPC (ФPC) VSS VDD VSS VDD VSS VDD VCM VCM

+Vref Vcm

  • Vref

ФS ФS ФS ФS ФS ФS ФA ФA SOP SOP CDAC CDAC

Vi+ Vi-

ФA ФA Vi+(n+1) Vi-(n+1) DC SDAC SDAC SPC (ФPC) IN IP

Vx+ Vx-

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SLIDE 15
  • Pre-charge switches closed
  • ZCD & current sources begin to turn on
  • Opamp output shorted to VCM
  • CDAC set to track output

VX+ VX-

CCLS CCLS

Vo+ Vo-

SPC (ФPC) VSS VDD VSS VDD VSS VDD VCM VCM

+Vref Vcm

  • Vref

ФS ФS ФS ФS ФS ФS ФA ФA SOP SOP CDAC CDAC

Vi+ Vi-

ФA ФA Vi+(n+1) Vi-(n+1) DC SDAC SDAC SPC (ФPC) IN IP

Vx+ Vx-

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SLIDE 16
  • ZCBC coarse charging
  • When ZCD trips:
  • turns off current sources
  • activates asynchronous timing block

VX+ VX-

CCLS CCLS

Vo+ Vo-

SPC (ФPC) VSS VDD VSS VDD VSS VDD VCM VCM

+Vref Vcm

  • Vref

ФS ФS ФS ФS ФS ФS ФA ФA SOP SOP CDAC CDAC

Vi+ Vi-

ФA ФA Vi+(n+1) Vi-(n+1) DC SDAC SDAC SPC (ФPC) IN IP

Vx+ Vx-

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SLIDE 17
  • Overshoot cancellation
  • ΔV on bottom plate of CDAC cancels overshoot

VX+ VX-

CCLS CCLS

Vo+ Vo-

SPC (ФPC) VSS VDD VSS VDD VSS VDD VCM VCM

+Vref Vcm

  • Vref

ФS ФS ФS ФS ФS ФS ФA ФA SOP SOP CDAC CDAC

Vi+ Vi-

ФA ФA Vi+(n+1) Vi-(n+1) DC SDAC SDAC SPC (ФPC) IN IP

Vx+ Vx-

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SLIDE 18
  • Opamp fine settling
  • Shorting switch (SOP) opens
  • CDAC disconnects from output (minimize load)

CCLS CCLS SPC (ФPC) VSS VDD VSS VDD VCM VCM

+Vref Vcm

  • Vref

ФS ФS ФS ФS ФS ФS ФA ФA SOP SOP

Vi+ Vi-

ФA ФA Vi+(n+1) Vi-(n+1) DC SPC (ФPC) IN IP

Vx+ Vx-

VX+ VX-

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SLIDE 19

Overshoot Cancellation

  • Pure ZCBC: signal independent portion becomes DC
  • ffset
  • Hybrid structure: opamp must cancel all overshoot

signal independent signal dependent

VX+ VX-

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SLIDE 20

Overshoot Cancellation

Opamp will try to cancel all overshoot present

VX+ VX- Opamp virtual ground condition: Vx- = Vx+

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SLIDE 21

Overshoot Cancellation

No cancellation: opamp output saturates

  • pamp
  • utputs

VX+ VX-

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SLIDE 22

Overshoot Cancellation

signal independent signal dependent

VX+ VX-

A solution: cancel all predictable overshoot

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SLIDE 23

Overshoot Cancellation

Opamp only processes signal dependent error

VX+ VX-

  • pamp
  • utputs
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SLIDE 24

Overshoot Cancellation

  • Charge cancellation DAC
  • Testability
  • No offset accumulation
  • Integrator compatible (e.g. ΔΣ)
  • Other possibilities to mitigate overshoot
  • ZCD input offset
  • Opamp input offset
  • Other DAC topologies
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SLIDE 25

Dynamic ZCD

Concept: redistribute current usage to maximize useful gm

time Current (Itail) time Voltage

Vi+

td

Vi- Vo-

low gm ok need high gm

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SLIDE 26

Dynamic ZCD

ΦPC Vi- Vi+ ΦPC Vo- Iref Vb Itail Vo+ VSS VDD M2 M1 CFB M3

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SLIDE 27

Dynamic ZCD

Vi- Vi+

ΦPC

Vo-

Iref

Vb Itail

Vo+ VSS VDD M2 M1 CFB M3

  • ff
  • ff

time

Current (Itail)

time

Input Voltage

Vi+ td Vi- Vo-

time

Output Voltage

ФPC td Vb Vo- td Itail

Step 1: Pre-charge

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SLIDE 28

Dynamic ZCD

Step 2: Power conservation

AZCD(Vi+ - Vi-) > (Vo+ - Vo-)

time

Current (Itail)

time

Input Voltage

Vi+ td Vi- Vo-

time

Output Voltage

td Vb Vo- td Itail

Vi- Vi+ Vo- Vb Itail

Vo+ VSS VDD M2 M1 CFB

  • ff
  • ff
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SLIDE 29

Dynamic ZCD

Step 3: High gm

AZCD(Vi+ - Vi-) < (Vo+ - Vo-)

time

Current (Itail)

time

Input Voltage

Vi+ td Vi- Vo-

time

Output Voltage

td Vb Vo- td Itail

Vi- Vi+ Vo- Vb Itail

Vo+ VSS VDD M2 M1 CFB

  • ff
  • ff
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SLIDE 30

Dynamic ZCD

Step 4: Shutdown

td

time

Current (Itail)

time

Input Voltage

Vi+ td Vi- Vo-

time

Output Voltage

td Vb Vo- Itail

Vi- Vi+ Vo- Vb

Vo+ VSS VDD M2 M1 CFB

  • ff
  • ff

Itail=0

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SLIDE 31

Dynamic ZCD

  • Strongly correlated design variables
  • AZCD
  • CFB
  • ISRC/CLOAD
  • Best choice dependent on specific design

targets

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SLIDE 32

ZCD Variation Tolerance

  • In test, Iref varied from 6.5uA - 50uA with no impact on

performance

  • Only limited by tuning range of test board
  • Current bias, voltage bias, or self-bias feasible
  • Higher gm at critical instant can suppress certain internal

and external variations

  • Floating bias
  • Blocks certain transient effects
  • Vulnerable to others
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SLIDE 33

ZCD Power Efficiency

  • Your mileage will vary
  • Depends on design specifications
  • Converter accuracy
  • ZCD time delay
  • Current source slew rate
  • For this test ADC: simulation shows 4x improvement
  • ver state of the art (Brooks, ISSCC 2009)
  • In general, the slower the ramp, the more dramatic the

savings

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SLIDE 34

Chip Micrograph

  • 10 identical 1.5b stages
  • 1.5b backend flash
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SLIDE 35

Measured Results

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SLIDE 36

Measured Results

10

  • 1

10 60 65 70 75

Fin / Fs dB

SNDR vs. Fin

fnyquist

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SLIDE 37

Measured Results

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SLIDE 38

Key Benefits

  • Accuracy - Extremely high effective gain, even in modern

processes.

  • Robustness - Relax ZCBC design by adding linear

feedback.

  • Efficiency - Amplification devices optimized for unique
  • requirements. Efficient charging with ZCBC. High gain,

single stage opamp w/o gain boosting amplifiers or compensation.

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SLIDE 39

Acknowledgements

  • This work was funded by the Semiconductor Research

Corporation and the Center for Design of Analog-Digital Integrated Circuits.

  • The authors would like to thank TowerJazz

Semiconductor for providing fabrication.

Additional thanks to Peter Kurahashi, Sasidhar Lingam, Phil Crosby, Arnie Frisch, Ed Hershberg, Dianne Glenn and members of the OSU AMS lab for their valuable contributions and insight.

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SLIDE 40

Additional Materials

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SLIDE 41

DNL

256 512 768 1024 1280 1536 1792 2048

  • 0.5

0.5

DIFFERENTIAL NONLINEARITY vs. DIGITAL OUTPUT CODE

DIGITAL OUTPUT CODE DNL (LSB)

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SLIDE 42

INL

256 512 768 1024 1280 1536 1792 2048

  • 3
  • 2
  • 1

1 2 3

INTEGRAL NONLINEARITY vs. DIGITAL OUTPUT CODE

DIGITAL OUTPUT CODE INL(LSB)

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SLIDE 43

Hypothesis for distortion issue

256 512 768 1024 1280 1536 1792 2048

  • 3
  • 2
  • 1

1 2 3

INTEGRAL NONLINEARITY vs. DIGITAL OUTPUT CODE

DIGITAL OUTPUT CODE INL(LSB)

  • Even harmonics not

seen in previous version of test board

  • Possibly originates

from off-chip

  • However, there is

also an on-chip explanation…

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SLIDE 44

Hypothesis for distortion issue

256 512 768 1024 1280 1536 1792 2048

  • 3
  • 2
  • 1

1 2 3

INTEGRAL NONLINEARITY vs. DIGITAL OUTPUT CODE

DIGITAL OUTPUT CODE INL(LSB)

  • If inputs begin too

close together (i.e. lowest codes), there will be a large variation in ZCD time delay

  • Need to be careful

that asymmetry of dynamic ZCD doesn’t cause an input offset that will worsen this performance “wall”

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SLIDE 45

Hypothesis for distortion issue

ΦPC Vi- Vi+ ΦPC Vo- Iref Vb Itail Vo+ VDD M2 M1 CFB CFB’ So+ So- Soff Soff VDD

Needed more analysis to determine the best value for the dummy load

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SLIDE 46

Overshoot Cancellation

  • Independent digital controls for each stage
  • Vo+ and Vo- DACs also independent
  • In measurement:
  • Used one universal DAC code
  • Conclusion: the stage-to-stage variation in signal

independent overshoot is small enough for a single global control

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SLIDE 47

Overshoot Cancellation (CDAC)

b7 VO VDD VSS b6 b5 b4 8C 4C 2C C b0 C SOP

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SLIDE 48

Overshoot Cancellation (CDAC)

b7 VO VDD VSS b6 b5 b4 8C 4C 2C C b0 C SOP

Step 1: Track ZCBC waveform

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SLIDE 49

Overshoot Cancellation (CDAC)

b7 VO VDD VSS b6 b5 b4 8C 4C 2C C b0 C SOP

Step 2: Cancel Overshoot

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SLIDE 50

Overshoot Cancellation (CDAC)

b7 VO VDD VSS b6 b5 b4 8C 4C 2C C b0 C SOP

Step 3: Remove load from output

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SLIDE 51

Dynamic ZCD (detail)

ΦPC Vi- Vi+ ΦPC Vo- Iref Vb Itail Vo+ VDD M2 M1 CFB CFB’ So+ So- Soff Soff VDD

Reset switches to reset kickback charge

dynamic inverters

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SLIDE 52

Dynamic ZCD (detail)

ΦPC Vi- Vi+ ΦPC Vo- Iref Vb Itail Vo+ VDD M2 M1 CFB CFB’ So+ So- Soff Soff VDD

Dummy load to match Vo+ load with Vo-

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SLIDE 53

Dynamic ZCD (detail)

ΦPC Vi- Vi+ ΦPC Vo- Iref Vb Itail Vo+ VDD M2 M1 CFB CFB’ So+ So- Soff Soff VDD

Pre-charge switches

During ФPC:

  • small Itail
  • small gm

→ too slow!

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SLIDE 54

Dynamic ZCD (detail)

ΦPC Vi- Vi+ ΦPC Vo- Iref Vb Itail Vo+ VDD M2 M1 CFB CFB’ So+ So- Soff Soff VDD

Pre-charge switches

ФPC Vo+ Vb Vo- VDD VSS

  • Theoretically possible to

guarantee Itail > 0 for any bias input