IEEE ISCAS 2015 Intro Architecture Circuits Design Results Conclusions 1/27 Class-AB Single-Stage OpAmp for Low-Power Switched-Capacitor Circuits S. Sutula 1 , M. Dei 1 , L. Terés 1,2 and F. Serra-Graells 1,2 stepan.sutula@imb-cnm.csic.es 1 Integrated Circuits and Systems (ICAS) Instituto de Microelectrónica de Barcelona, IMB-CNM(CSIC) 2 Dept. of Microelectronics and Electronic Systems (DEMISE) Universitat Autònoma de Barcelona (UAB) Lisbon, May 2015 IMB-CNM(CSIC) S. Sutula et al. DEMISE(UAB)
IEEE ISCAS 2015 Intro Architecture Circuits Design Results Conclusions 2/27 1 Introduction 2 Class-AB Architecture 3 Process-Independent Circuits 4 Practical Design 5 Experimental Results 6 Conclusions IMB-CNM(CSIC) S. Sutula et al. DEMISE(UAB)
IEEE ISCAS 2015 Intro Architecture Circuits Design Results Conclusions 3/27 1 Introduction 2 Class-AB Architecture 3 Process-Independent Circuits 4 Practical Design 5 Experimental Results 6 Conclusions IMB-CNM(CSIC) S. Sutula et al. DEMISE(UAB)
IEEE ISCAS 2015 Intro Architecture Circuits Design Results Conclusions 4/27 Low-Power Switched-Capacitor Design Low-Voltage Approach Low-Current Approach ◮ Bulk-driven OpAmps ◮ Telescopic diff. pairs with LCMFB ◮ Internal supply multipliers ◮ Dynamic biasing by RC bias ◮ Inverter-based OpAmps tees ◮ Switched OpAmps ◮ Hybrid-Class-A/AB ◮ Adaptive biasing ◮ Nominal-voltage downscaling ◮ Higher power savings ◭ Moderate power savings ◭ Parameter-variation sensitivity IMB-CNM(CSIC) S. Sutula et al. DEMISE(UAB)
IEEE ISCAS 2015 Intro Architecture Circuits Design Results Conclusions 5/27 1 Introduction 2 Class-AB Architecture 3 Process-Independent Circuits 4 Practical Design 5 Experimental Results 6 Conclusions IMB-CNM(CSIC) S. Sutula et al. DEMISE(UAB)
IEEE ISCAS 2015 Intro Architecture Circuits Design Results Conclusions 6/27 Single-Stage Class-AB OpAmp ◮ Two complementary diff. pairs ◮ Dynamic current mirrors ◮ Separate Class-AB control ◮ Partial positive feedback ◮ CMFB control through the NMOS-pair tail ◮ Gain improvement by the output cascode transistors ◮ No need for the Miller compensation capacitors ◮ High-peak Class-AB currents only in the output transistors IMB-CNM(CSIC) S. Sutula et al. DEMISE(UAB)
IEEE ISCAS 2015 Intro Architecture Circuits Design Results Conclusions 7/27 Single-Stage Class-AB OpAmp ◮ Supposing all boxed devices operating in strong inversion: AB D . = A + B � � � I inp n β I onp = + V cp D A 2 ◮ Desired Class-AB behavior: I outp ≡ 0 V cp ≡ V xp I onp ≡ I inp � I onp ≪ I inp I outp �≡ 0 V cp �≡ V xp I onp ≫ I inp IMB-CNM(CSIC) S. Sutula et al. DEMISE(UAB)
IEEE ISCAS 2015 Intro Architecture Circuits Design Results Conclusions 8/27 1 Introduction 2 Class-AB Architecture 3 Process-Independent Circuits 4 Practical Design 5 Experimental Results 6 Conclusions IMB-CNM(CSIC) S. Sutula et al. DEMISE(UAB)
IEEE ISCAS 2015 Intro Architecture Circuits Design Results Conclusions 9/27 Type I � ��� � � � ◮ Cross-coupled pair � � I inp I inp I onp I onp I inp = B I onn 2 − + − D D A D A for the Class-AB �� � � � � I inp � operation 2 I tail I onp I inn I onn +C − − + + D D D A A �� � � � I inp � I onp I inn I onn ◮ Crossing transistor as − − + D D A A a Class-AB limiter ◮ Independence from the technology parameters ◭ Need for an extra bias reference IMB-CNM(CSIC) S. Sutula et al. DEMISE(UAB)
IEEE ISCAS 2015 Intro Architecture Circuits Design Results Conclusions 10/27 Type I with Class-AB Smoother ◮ Low-level common-mode current injection ◮ Instability prevention under a high Class-AB modulation ◭ Need for extra current sources IMB-CNM(CSIC) S. Sutula et al. DEMISE(UAB)
IEEE ISCAS 2015 Intro Architecture Circuits Design Results Conclusions 11/27 Type II � � � � � I onp I inp = I onn 2 B +C D D ◮ Independence from the technology parameters �� ���� � � � I inp I inp I onp I onp − (B+C) − − D A D A ◮ Auto-biased Class-AB limiter 1+ A D . = A(B+C) I max ≃ B+C I tail > I tail C A+B+C A 1+ ◮ Self-latch prevention ◮ Simple sizing procedure IMB-CNM(CSIC) S. Sutula et al. DEMISE(UAB)
IEEE ISCAS 2015 Intro Architecture Circuits Design Results Conclusions 12/27 1 Introduction 2 Class-AB Architecture 3 Process-Independent Circuits 4 Practical Design 5 Experimental Results 6 Conclusions IMB-CNM(CSIC) S. Sutula et al. DEMISE(UAB)
IEEE ISCAS 2015 Intro Architecture Circuits Design Results Conclusions 13/27 Type-II OpAmp Using a 0.18-µm CMOS Technology ◮ Circuit design based on the inversion-coefficient ◮ Reduced set of transistor matching groups ◮ Minimum-channel-length devices can be used ◮ Bias for cascode transistors optimized for maximum output full scale ◮ 1.8-V nominal voltage supply of the CMOS technology IMB-CNM(CSIC) S. Sutula et al. DEMISE(UAB)
IEEE ISCAS 2015 Intro Architecture Circuits Design Results Conclusions 14/27 Simulation Results 10 ◮ DC transfer curve Analytical Numerical 8 ◮ Analytical versus numerical behavior 6 [mA] I onn I onp ◮ Class-AB achieves 4 about × 4 bias current 2 0 − 1 − 0.5 0 0.5 1 I inp − I inn [ mA] IMB-CNM(CSIC) S. Sutula et al. DEMISE(UAB)
IEEE ISCAS 2015 Intro Architecture Circuits Design Results Conclusions 15/27 Simulation Results 0 ◮ Frequency Phase 80 response Gain 70 ◮ 200-pF load Differential Gain [dB] 60 − 60 capacitance 50 Phase [°] 40 72 dB 30 − 120 20 50 ° 10 0 − 180 10 3 10 4 10 5 10 6 10 7 10 8 10 9 Frequency [Hz] IMB-CNM(CSIC) S. Sutula et al. DEMISE(UAB)
IEEE ISCAS 2015 Intro Architecture Circuits Design Results Conclusions 16/27 Simulation Results ◮ Step response for several load conditions 2 Differential Output Voltage [V] 650 µF at 1 Hz, 650 nF at 1 kHz 650 pF at 1 MHz 1 0 − 1 0 0 . 2 0 . 4 0 . 6 0 . 8 1 1 . 2 1 . 4 1 . 6 1 . 8 2 Time × Input Frequency [-] ◮ Stability robustness IMB-CNM(CSIC) S. Sutula et al. DEMISE(UAB)
IEEE ISCAS 2015 Intro Architecture Circuits Design Results Conclusions 17/27 Integration ◮ Standard 0.18-µm 1P6M CMOS technology ◮ 0.07-mm 2 area ◮ Additional CMFB averaging capacitors for SC applications IMB-CNM(CSIC) S. Sutula et al. DEMISE(UAB)
IEEE ISCAS 2015 Intro Architecture Circuits Design Results Conclusions 18/27 Integration ◮ Standard 0.18-µm 1P6M CMOS technology ◮ 0.07-mm 2 area ◮ Additional CMFB averaging capacitors for SC applications IMB-CNM(CSIC) S. Sutula et al. DEMISE(UAB)
IEEE ISCAS 2015 Intro Architecture Circuits Design Results Conclusions 19/27 1 Introduction 2 Class-AB Architecture 3 Process-Independent Circuits 4 Practical Design 5 Experimental Results 6 Conclusions IMB-CNM(CSIC) S. Sutula et al. DEMISE(UAB)
IEEE ISCAS 2015 Intro Architecture Circuits Design Results Conclusions 20/27 Step Response ] Simulated V 1 Di ff . Output Voltage [ Measured 0 − 1 I supply Current [mA] 10 5 I opp I opn 0 0 . 2 0 . 4 0 . 6 0 . 8 1 . 2 1 . 4 1 . 6 1 . 8 0 1 2 Time [ms] IMB-CNM(CSIC) S. Sutula et al. DEMISE(UAB)
IEEE ISCAS 2015 Intro Architecture Circuits Design Results Conclusions 21/27 Full-Scale Evaluation 2 Differential Output Voltage [V] Ideal Simulated 1 Measured 0 − 1 − 2 0 20 40 60 80 100 120 140 160 180 200 Time [ms] ◮ 3.3-V pp differential full scale at 1.8-V voltage supply IMB-CNM(CSIC) S. Sutula et al. DEMISE(UAB)
IEEE ISCAS 2015 Intro Architecture Circuits Design Results Conclusions 22/27 Figure-of-Merit Comparison This Parameter [1] [2] [3] [4] [5] Units work Technology 0.5 0.5 0.25 0.13 0.18 0.18 µm Supply 2 2 1.2 1.2 0.8 1.8 V DC gain 43 45 69 70 51 72 dB 80 25 4 5.5 8 200 pF C load GBW 0.725 11 165 35 0.057 86.5 MHz Phase margin 89.5 N/A 65 45 60 50 ° Slew rate, SR 89 20 329 19.5 0.14 74.1 V/µs Static power, P 0.12 0.04 5.8 0.11 0.0012 11.9 mW mm 2 Area 0.024 0.012 N/A 0.012 0.057 0.07 pF V 59.33 12.50 0.28 0.98 0.93 1.25 FOM µs µW � � pF FOM = SR · C load V µs µW P IMB-CNM(CSIC) S. Sutula et al. DEMISE(UAB)
IEEE ISCAS 2015 Intro Architecture Circuits Design Results Conclusions 23/27 1 Introduction 2 Class-AB Architecture 3 Process-Independent Circuits 4 Practical Design 5 Experimental Results 6 Conclusions IMB-CNM(CSIC) S. Sutula et al. DEMISE(UAB)
IEEE ISCAS 2015 Intro Architecture Circuits Design Results Conclusions 24/27 Conclusions ◮ New family of Class-AB OpAmps ◮ Single-stage topology ◮ No need for an internal frequency compensation ◮ Class-AB current peaks in the output transistors only ◮ Low sensitivity to the technology parameter variations ◮ Simple analytical design flow ◮ Successfully used in a 16-bit 100-kS/s ΔΣ ADC Thank you! IMB-CNM(CSIC) S. Sutula et al. DEMISE(UAB)
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