Opamp Design Project Help Session Boise, 19/Apr/2014 Vishal Saxena - - PowerPoint PPT Presentation

Vishal Saxena <vishalsaxena@boisestate.edu>

Opamp Design Project Help Session

Boise, 19/Apr/2014 Vishal Saxena

Vishal Saxena <vishalsaxena@boisestate.edu>

Design Specifications

Vishal Saxena <vishalsaxena@boisestate.edu>

Two-Stage Opamp

Vishal Saxena <vishalsaxena@boisestate.edu>

Two-Stage Opamp

Vishal Saxena <vishalsaxena@boisestate.edu>

Design Equations

Vishal Saxena <vishalsaxena@boisestate.edu>

Two-Stage Opamp –Zero-Nulling R

Vishal Saxena <vishalsaxena@boisestate.edu>

Two-Stage Opamp –Voltage Buffer Compensation

Vishal Saxena <vishalsaxena@boisestate.edu>

Two-Stage Opamp –Common Gate Compensation

Vishal Saxena <vishalsaxena@boisestate.edu>

Class-A Stage: Slewing

Vishal Saxena <vishalsaxena@boisestate.edu>

Class-AB Stage: Floating Current Mirror

Vishal Saxena <vishalsaxena@boisestate.edu>

Two-Stage Opamp –Telescopic with Class- AB Stage

Vishal Saxena <vishalsaxena@boisestate.edu>

Folded Cascode OTA

Vishal Saxena <vishalsaxena@boisestate.edu>

Two-Stage Opamp –Folded-Cascode with Class-AB Stage

Vishal Saxena <vishalsaxena@boisestate.edu>

Two-Stage Opamp –Folded-Cascode + Class-AB Stage, Full-rail input CMR

Vishal Saxena <vishalsaxena@boisestate.edu>

Two-Stage Opamp –Gain Enhancement

Vishal Saxena <vishalsaxena@boisestate.edu>

Two-Stage Opamp –AC Response

Caveat:

• Don’t use this method.
• Use STB analysis with iprobe

instead.

Vishal Saxena <vishalsaxena@boisestate.edu>

Two-Stage Opamp –Step Response

Vishal Saxena <vishalsaxena@boisestate.edu>

Spectre STB Analysis

• The STB analysis linearizes the circuit about the DC operating point and

computes the loop-gain, gain and phase margins (if the sweep variable is frequency), for a feedback loop or a gain device [1].

• Refer to the Spectre Simulation Refrence [1] and [2] for details.

Vishal Saxena <vishalsaxena@boisestate.edu>

Example Single-ended Opamp Schematic

Vishal Saxena <vishalsaxena@boisestate.edu>

STB Analysis Test Bench

• Pay attention to the iprobe component (from analogLib)
• Acts as a short for DC, but breaks the loop in stb analysis
• Place the probe at a point where it completely breaks (all) the

loop(s).

Vishal Saxena <vishalsaxena@boisestate.edu>

DC Annotation

• Annotating the node voltages and DC operating points of the

devices helps debug the design

• Check device gds to see if its in triode or saturation regions

Vishal Saxena <vishalsaxena@boisestate.edu>

Simulation Setup

• Always have dc analysis on for debugging purpose

Vishal Saxena <vishalsaxena@boisestate.edu>

Bode Plot Setup

• Results->Direct Plot-> Main Form

Vishal Saxena <vishalsaxena@boisestate.edu>

Open Loop Response Bode Plots

• Here, fun=152.5 MHz, PM=41.8º
• Try to use the stb analysis while the circuit is in the

desired feedback configuration

• Break the loop with realistic DC operation points

Vishal Saxena <vishalsaxena@boisestate.edu>

Transient Step Response Test Bench

• Transient step-response verifies the closed-loop stability
• Use small as wells as large steps for characterization
• iprobe acts as a short (can remove it)

Vishal Saxena <vishalsaxena@boisestate.edu>

Small Step Response

• Observe the ringing (PM was 41º)
• Compensate more

Vishal Saxena <vishalsaxena@boisestate.edu>

Large Step Response

• Note the slewing in the output

Vishal Saxena <vishalsaxena@boisestate.edu>

Miller Compensation

1 2

vm

v p

vout

Vbias4

Vbias3

CC 10pF

Unlabeled NMOS are 10/2. Unlabeled PMOS are 22/2.

VDD VDD VDD

30pF

CL

M3 M4 M1 M2 M6TL M6BL M6TR M6BR M8T M8B M7 220/2 100/2 100/2 x10 750Ω

iC fb iC ff

• Compensation capacitor (Cc) between

the output of the gain stages causes pole-splitting and achieves dominant pole compensation.

• An RHP zero exists at
• Due to feed-forward component of

the compensation current (iC).

• The second pole is located at
• The unity-gain frequency is
• A benign undershoot in step-

response due to the RHP zero

All the op-amps presented have been designed in AMI C5N 0.5μm CMOS process with scale=0.3 μm and Lmin=2. The op-amps drive a 30pF off-chip load offered by the test-setup.

Vishal Saxena <vishalsaxena@boisestate.edu>

Saxena

Drawbacks of Direct (Miller) Compensation

• The RHP zero decreases phase

margin

• Requires large CC for

compensation (10pF here for a 30pF load!).

• Slow-speed for a given load, CL.
• Poor PSRR
• Supply noise feeds to the
• utput through CC.
• Large layout size.

1 2

vm v p vout Vbias4 Vbias3 CC

10pF Unlabeled NMOS are 10/2. Unlabeled PMOS are 22/2.

VDD VDD VDD

30pF

CL

M3 M4 M1 M2 M6TL M6BL M6TR M6BR M8T M8B M7 220/2 100/2 100/2 x10

Vishal Saxena <vishalsaxena@boisestate.edu>

Saxena

Indirect (or Ahuja) Compensation

• The RHP zero can be eliminated by

blocking the feed-forward compensation current component by using

• A common gate stage,
• A voltage buffer,
• Common gate “embedded” in the

cascode diff-amp, or

• A current mirror buffer.
• Now, the compensation current is

fed-back from the output to node-1 indirectly through a low-Z node-A.

• Since node-1 is not loaded by CC,

this results in higher unity-gain frequency (fun).

An indirect-compensated op-amp using a common-gate stage.

1 2 Unlabeled NMOS are 10/2. Unlabeled PMOS are 22/2.

VDD VDD VDD

30pF 220/2 100/2 100/2 x10

VDD

Vbias3 Vbias4 vm vp vout Cc CL ic MCG

A M3 M4 M1 M6TL M6BL M6TR M6BR M8T M8B M7 M2 M9 M10T M10B

Vishal Saxena <vishalsaxena@boisestate.edu>

Saxena

Indirect Compensation in a Cascoded Op- amp

1 2

vm v p vout CC

1.5pF Unlabeled NMOS are 10/2. Unlabeled PMOS are 44/2.

VDD VDD VDD

30pF

CL

Vbias2 Vbias3 Vbias4

A 50/2 50/2 110/2 M1 M2 M6TL M6BL M6TR M6BR M3T M3B M4T M4B M8T M8B M7

ic

Indirect-compensation using cascoded current mirror load.

1 2

vm v p vout CC

1.5pF Unlabeled NMOS are 10/2. Unlabeled PMOS are 22/2.

VDD VDD VDD

30pF

CL

Vbias3 Vbias4

A 100/2 100/2 220/2 M1B M2B M5T M5B M3 M1T M4 M2T M8T M8B M7

VDD

M4

Vbias1

30/2 30/2 10/10

ic

Indirect-compensation using cascoded diff-pair.

 Employing the common gate device “embedded” in the cascode structure for indirect compensation avoids a separate buffer stage.

 Lower power consumption.  Also voltage buffer reduces the swing which is avoided here.

Vishal Saxena <vishalsaxena@boisestate.edu>

Saxena

Analytical Modeling of Indirect Compensation

A1 A2 Cc

1 2

vin vout

Differential Amplifier Gain Stage

Rc

A

ic

Block Diagram Small signal analytical model

RC is the resistance attached to node-A.

ic vout sCc Rc   1

+

• +
• 1

2

gm1vs gm2v1 R1 C1 R2 C2 vout Cc Rc

The compensation current (iC) is indirectly fed-back to node-1.

Vishal Saxena <vishalsaxena@boisestate.edu>

Saxena

Analytical Results for Indirect Compensation

j 

z1  un p1 p2 p3

Pole-zero plot

 Pole p2 is much farther away from fun.

 Can use smaller gm2=>less power!

 LHP zero improves phase margin.  Much faster op-amp with lower power and smaller CC.  Better slew rate as CC is smaller.

LHP zero

Vishal Saxena <vishalsaxena@boisestate.edu>

Saxena

Indirect Compensation Using Split-Length Devices

• As VDD scales down, cascoding is becoming tough. Then how

to realize indirect compensation as we have no low-Z node available?

• Solution: Employ split-length devices to create a low-Z node.
• Creates a pseudo-cascode stack but its really a single device.
• In the NMOS case, the lower device is always in triode hence

node-A is a low-Z node. Similarly for the PMOS, node-A is low-Z.

A

VDD

M1T W/L1 M1B W/L2 M1 W/(L1+L2)

Equivalent

M1T W/L1 M1B W/L2 M1 W/(L1+L2)

VDD

Triode Triode Low-Z node Low-Z node

Equivalent A

NMOS PMOS Split-length 44/4(=22/2) PMOS layout

S D A

Low-Z node

G

Vishal Saxena <vishalsaxena@boisestate.edu>

Saxena

Split-Length Current Mirror Load (SLCL) Op-amp

1 2

vm v p vout Vbias4 Vbias3 CC

2pF Unlabeled NMOS are 10/2. Unlabeled PMOS are 22/2.

VDD VDD VDD

30pF

CL

M3B M4B M1 M2 M6TL M6BL M6TR M6BR M8T M8B M7T M3T M4T M7B 50/2 50/2 220/2 220/2 A

ic

fun z1 p2,3

 The current mirror load devices are split-length to create low-Z node-A.  Here, fun=20MHz, PM=75° and ts=60ns.

ts

Frequency Response Small step-input settling in follower configuration

Vishal Saxena <vishalsaxena@boisestate.edu>

Saxena

SLCL Op-amp Analysis

1 2

vout

A

1 gmp

id1 id2

vs 2 1 gmp gm vs 1 2

+

• 

vs 2

CL Cc v=0

1 2

vout

A

1 gmp

id1

vs 2

CL Cc

 g g v

m mp s 1

(a) (b)

+

• +
• 1

2

gm2v1 R1 C1 vout Cc v1 rop CA +

• vsgA

C2 R2

A

 g g v

m mp s 1

1 gmp

gmpvsgA

ic vout sCc gmp   1 1

+

• +
• 1

2

gm2v1 R1 C1 vout Cc v1 C2 R2 ic

gm vs 1 1 gmp gm vs 1 2 1 gmp

 Here fz1=3.77fun

 LHP zero appears at a higher frequency than fun.

Vishal Saxena <vishalsaxena@boisestate.edu>

Saxena

Split-Length Diff-Pair (SLDP) Op-amp

 The diff-pair devices are split-length to create low-Z node-A.  Here, fun=35MHz, PM=62°, ts=75ns.  Better PSRR due to isolation of node-A from the supply rails.

Frequency Response Small step-input settling in follower configuration

1 2

vm v p

vout

Vbias4

Vbias3

CC

2pF Unlabeled NMOS are 10/2. Unlabeled PMOS are 22/2.

VDD VDD VDD

30pF

CL

M3 M4 M1B M2B M6TL M6BL M6TR M6BR M8T M8B M7 M1T M2T 20/2 20/2 20/2 20/2

ic

110/2 50/2 50/2 A

fun p2,3 z1

ts

Vishal Saxena <vishalsaxena@boisestate.edu>

Saxena

SLDP Op-amp Analysis

1 2

vout

A

id1 id2

vs 2  vs 2

CL Cc v=0

1 gmn 1 gmn

1 2

vout

A

id2

vs 2

CL Cc

1 gmn

rop (a) (b)

id gmnvs 2 4  

 Here fz1=0.94fun,

 LHP zero appears slightly before fun and flattens the magnitude response.  This may degrade the phase margin.

 Not as good as SLCL, but is of great utility in multi-stage op-amp design due to higher PSRR.

+

• +
• 1

2

gm2v1 CA vout vA ron C1 +

• vgs1

C2 R2

A

gmnvgs1

vs 2 1 gmn

R1

gmnvs 4

Cc

1 gmn ic vout sCc gmn   1 1

+

• +
• 1

2

gm2v1 R1 C1 vout Cc v1 C2 R2 ic

gmnvs 2 1 gmn

Vishal Saxena <vishalsaxena@boisestate.edu>

Saxena

Test Chip 1: Two-stage Op-amps

Miller 3-Stage Indirect SLCL Indirect SLDP Indirect Miller with Rz

 AMI C5N 0.5μm CMOS, 1.5mmX1.5mm die size.

Vishal Saxena <vishalsaxena@boisestate.edu>

Saxena

• Test Results and Performance Comparison

vin vout

vin vout

vin vout

Miller with Rz (ts=250ns) SLCL Indirect (ts=60ns) SLDP Indirect (ts=75ns)

Performance comparison of the op-amps for CL=30pF.

 10X gain bandwidth (fun).  4X faster settling time.  55% smaller layout area.  40% less power consumption.

Vishal Saxena <vishalsaxena@boisestate.edu>

Saxena

Effect of LHP-zero on Settling

 In certain cases with indirect compensation, the LHP-zero (ωz,LHP) shows up near fun.

 Causes gain flattening and degrades PM  Hard to push out due to topology restrictions

 Ringing in closed-loop step response

 This ringing is uncharacteristic of the 2nd order system.  Used to be a benign undershoot with the RHP zero, here it can be pesky  Is this settling behavior acceptable?

 Watch out for the ωz,LHP for clean settling behavior!

Frequency Response Small step-input settling in follower configuration

• 40
• 20

20 40 60 80 Magnitude (dB) 10

2

10

4

10

6

10

8

45 90 135 180 Phase (deg) Bode Diagram Frequency (Hz)

0.2 0.4 0.6 0.8 1 1.2 x 10

• 7

0.1 0.2 0.3 0.4 0.5 0.6 0.7 0.8 0.9 1 Closed Loop Step Response Time (sec) Amplitude

Caveat:

• When using indirect

compensation be aware of the LHP-zero induced transient settling issues

Vishal Saxena <vishalsaxena@boisestate.edu>

References

[1] Spectre User Simulation Guide, pages 160-165 http://www.designers-guide.org/Forum/YaBB.pl?num=1170321868 [2] M. Tian, V. Viswanathan, J. Hangtan, K. Kundert, “Striving for Small-Signal Stability: Loop- based and Device-based Algorithms for Stability Analysis of Linear Analog Circuits in the Frequency Domain,” Circuits and Devices, Jan 2001. http://www.kenkundert.com/docs/cd2001-01.pdf [3] https://secure.engr.oregonstate.edu/wiki/ams/index.php/Spectre/STB