Analog Integrated Circuits Fundamental Building Blocks Fundamental - - PowerPoint PPT Presentation

Analog Integrated Circuits Fundamental Building Blocks

Faculty of Electronics Telecommunications and Information Technology

Fundamental Building Blocks

Basic OTA/Opamp architectures

Information Technology

Gabor Csipkes

Bases of Electronics Department

Outline

 definition of the OTA/opamp  cascade of amplifier stages – the general opamp architecture  the uncompensated Miller opamp – small signal model at low and high frequencies  the uncompensated Miller opamp – small signal model at low and high frequencies  step response of a second order system with unity feedback  the two stage opamp with Miller compensation – models and parameters  sizing algorithm for the two stage Miller opamp  the telescopic opamp – voltage budget, models and parameters

Analog Integrated Circuits – Fundamental building blocks – Basic OTA/Opamp architectures 2

 sizing algorithm of the telescopic opamp  the folded cascode opamp – small signal low and high frequency model  sizing algorithm for the folded cascode opamp

The ideal opamp - definitions

 ideal opamp = a differential input, voltage controlled voltage source with very large

• pen loop gain

 the ideal gain is frequency independent, but real gain can be modeled with a set of poles and zeros → typically low pass behavior  very large input resistance and near zero output resistance  opamps with strictly capacitive loads can have large output resistance → Operational Transconductance Amplifiers (OTA) often also called opamp  the output may be single ended (referenced to ground) or differential  single or symmetrical supply voltages

Analog Integrated Circuits – Fundamental building blocks – Basic OTA/Opamp architectures 3

 

• ut

V a V V

 

 

The opamp – a cascade of elementary stages

 the typical opamp architecture → a differential amplifier followed by a high gain inverting stage and a voltage follower for low output impedance  the voltage follower may be missing if the load is known to be strictly capacitive  frequency compensation for closed loop stability probably required (more on this later)  frequency compensation for closed loop stability probably required (more on this later)  elementary amplifier stages → subsequent V-I and I-V conversions  most simple form → the two stage opamp

V-I I-V

Analog Integrated Circuits – Fundamental building blocks – Basic OTA/Opamp architectures 4

cascade of elementary stages V-I I-V I-V

The two stage or Miller opamp

Analog Integrated Circuits – Fundamental building blocks – Basic OTA/Opamp architectures 5

The two stage opamp

 the small signal low frequency model with two equivalent stages  no capacitive effects → low frequency or DC voltage gain  each stage can be analyzed individually → Gm and Rout specific to each configuration V

1 1,2 m m

G g  

Analog Integrated Circuits – Fundamental building blocks – Basic OTA/Opamp architectures 6

1 1,2 1 2 4 2 6 2 6 7

|| ||

m m

• ut

DS DS m m

• ut

DS DS

G g R r r G g R r r           

1 2

1 1 2 2 m

• ut

m

• ut

a a

a G R G R          

The two stage opamp

 the small signal high frequency model → consider load and parasitic capacitances V

1 2 1,2 3 3 4 1 3 GD GS GS DB DB

C C C C C C C C C C            

V

4 4 5 6 2 4 6 6 7 6 7 GD GS DB DB GD L DB DB L

C C C C C C C C C C C C C                 

  

1 5 2 7

( ) 1 1

• ut
• ut

a a s sR C sR C   

Analog Integrated Circuits – Fundamental building blocks – Basic OTA/Opamp architectures 7

The frequency response is dominated by C5 and C7 due to the large Rout1 and Rout2 !

  

1 5 2 7

1 1

• ut
• ut

sR C sR C  

The two stage opamp – with negative feedback

 the closed loop model of an opamp with negative feedback

( ) ( ) 1 ( ) a s A s a s r    ( ) 1 1 a a s s s                 

 

 

 

1 2 2 1 2 1 2

1 1 ( ) ( ) 1 ( ) 1

p p p p p p

a a r a r a s A s a s r s s a r                 

1 2 p p

       

The closed loop gain: The standard form of a second order transfer function:

2

( )

n

A A s   

Analog Integrated Circuits – Fundamental building blocks – Basic OTA/Opamp architectures 8

The standard form of a second order transfer function: (DC gain A0, resonant frequency ωn and damping factor ξ )

2 2

( ) 2

n n n

A A s s s       

   

1 2 1 2 1 2

1 ; 1 ; 1 2 1

p p n p p p p

a A a r a r r a r                

Frequency response of a second order system

 the effect of the feedback transmittance r on the magnitude response



A0 decreases with r

1 A r 



Analog Integrated Circuits – Fundamental building blocks – Basic OTA/Opamp architectures 9

• Overshoot of the frequency response at ωn →

complex poles → under damped step response

• worst case stability for unity gain (r=1 and

A0=1) → lowest ξ for given a0, ωp1 and ωp2

Step response for unity gain feedback

 the time domain step response is calculated as  damping of the oscillation amplitude depends on ξ  typically, if poles ωp1 and ωp2 are close to each other ξ<1 → under damped system with fading oscillations of the step response

1

( ) ( )

• ut

A s V t s

 

      L

fading oscillations of the step response

2 2 2

1 ( ) 1 sin 1 arctan 1

nt

• ut

n

e V t t

 

    



                           

• scillations with the period

fading exponential

Analog Integrated Circuits – Fundamental building blocks – Basic OTA/Opamp architectures 10

 since the sin function varies between -1 and 1 → time domain overshoot around the unit step → the overshoot and number of cycles until settling increases with a smaller ξ

• scillations with the period

depending on ωn and ξ fading exponential envelope

Step response for unity gain feedback

 step response of the two stage opamp in unity gain feedback configuration

 

• ptimal

 

• ptimal

response

Analog Integrated Circuits – Fundamental building blocks – Basic OTA/Opamp architectures 11

 the circuit is unusable as amplifier for small ξ due to the very long settling time  the response stability depends on the phase margin (mφ) → optimal response for mφ=65°

 

Stability and phase margin

 closed loop gain for unity feedback:  the closed loop gain approaches ∞ → even for no input any perturbation is amplified with under damped transients → sustained oscillations occur, feedback turns positive and

( ) ( ) 1 ( ) a s A s a s  

What if denominator is 0 ???

( ) 1 a s  

with under damped transients → sustained oscillations occur, feedback turns positive and system becomes unstable  Barkhausen's stability criteria:

( ) 1 ( ) 180 a j a j           

1 2

1 1 1

p p

a j j                   

0dB

f

solve for ω

Analog Integrated Circuits – Fundamental building blocks – Basic OTA/Opamp architectures 12 1 2 p p

       

 

1 2

180 180 arctan arctan

• dB

dB dB p p

m a j



                           

Pole locations and phase margin

 the relation between pole frequencies and f0dB defines mφ and the stability of the step response This is what we need ! we need !

Analog Integrated Circuits – Fundamental building blocks – Basic OTA/Opamp architectures 13 2

45

p dB

f f m   

2

45

p dB

f f m   

2

45

p dB

f f m   

Frequency compensation

 need fp2>f0dB so that mφ>45° → impossible to achieve by simply cascading a differential amplifier and a common source inverting amplifier

1

1 2

p

f R C     

Typically:

R R  

1 1 5 2 2 7

2 1 2

p

• ut

p

• ut

R C f R C         

fp1 and fp2 are close to each other !!!

1 2 7 5

• ut
• ut

R R C C     

Analog Integrated Circuits – Fundamental building blocks – Basic OTA/Opamp architectures 14

We need to manipulate pole locations to separate fp1 and fp2 → → frequency compensation

Miller frequency compensation

 idea 1: push p1 to lower frequencies by increasing C5 → must have very large values for a satisfactory mφ → not practical for the integrated opamp  idea 2: use the Miller effect to virtually increase C5 → practical solution since the gain of the second stage is usually large → connect CM that emphasizes the capacitive shunt around the inverting second stage the inverting second stage

V 

Analog Integrated Circuits – Fundamental building blocks – Basic OTA/Opamp architectures 15

   

1 5 1 2 2 m in M

• ut
• ut
• ut

m L

• ut

M

• ut
• ut

V G V sC V sC V V R V G V sC V sC V V R                

Miller frequency compensation

 capacitances C1,C2, C3,C4 and C6 considered small and neglected for simplicity  the frequency dependent gain a(s) results:

1

M

C G G R R s       

 use the dominant pole approximation to find pole and zero locations

   

1 2 1 2 2 2 2 1 2 1 2 5 5 1 1 5 2 1 2 2 1 2

1 ( ) 1

M m m

• ut
• ut

m

• ut
• ut

L M L M

• ut
• ut

L

• ut
• ut

M m

• ut
• ut

M

C G G R R s G a s k s k s k R R C C C C C C k R C R C R R C G R R C                        

dominant terms

Analog Integrated Circuits – Fundamental building blocks – Basic OTA/Opamp architectures 16 1 2 1 2 2 2 1 2 2 1 2

1 ( ) 1

M m m

• ut
• ut

m

• ut
• ut

L M m

• ut
• ut

M

C G G R R s G a s R R C C s G R R C s          

1 2

1 ( ) 1 1

zp p p

s a a s s s                           

Miller compensation – frequency response

One dominant pole, one high frequency pole and one right half plane zero:

1 2 1 2 1( ) 2 2 1 2 2 2

1 2 2

m m

• ut
• ut

p d m

• ut
• ut

M m p L m

a G G R R f G R R C G f C G f                

Analog Integrated Circuits – Fundamental building blocks – Basic OTA/Opamp architectures 17 2

2

m zp M

G f C     

1 1( )

2

m p d M

G GBW a f C    

2

90 arctan arctan

p zp

GBW GBW m f f



                  

Miller compensation – step response

V SR t   

 assume unity gain negative feedback and apply an input step to the follower  step response calculated as  Slew Rate (SR) → variation rate of the output voltage

1

( ) ( )

• ut

A s V t s

 

      L

t 

Analog Integrated Circuits – Fundamental building blocks – Basic OTA/Opamp architectures 18

The two stage compensated opamp – slew rate

 the total capacitance of every node must be charged and discharged in each cycle  charging rate depends on the largest supplied current  every node limits the variation rate of V

• ut → the slew rate is imposed by the most

stringent limitation

 

1 2 5 7 1 2

min , ;

• ut

M L

V SR SR SR t I I SR SR C C             

stringent limitation Typically I5<<I7, while CM and

Analog Integrated Circuits – Fundamental building blocks – Basic OTA/Opamp architectures 19 5 M

I SR C 

Typically I5<<I7, while CM and CL are comparable

The two stage opamp design algorithm

 specifications given (others are also possible)

• the low frequency open loop gain a0 larger than a critical value
• slew rate (SR)
• slew rate (SR)
• unity-gain bandwidth (GBW)
• the right half plane zero frequency relative to GBW (ratio k imposed by the

designer!)

• the typical load capacitance CL
• supply voltages

Analog Integrated Circuits – Fundamental building blocks – Basic OTA/Opamp architectures 20

• supply voltages
• phase margin mφ chosen according to the application (often unconditional stability !)
• typical transistor VDSat voltages (unless resulting from design constraints ! )

The two stage opamp design algorithm

1

2

m M

G GBW C G       

 Step 1 → calculate the required compensation capacitor CM relative to CL

1

2

m M

G GBW C G        

2

2

m zp M

G f k GBW C        

 

1 , , tan 90 arctan GBW m f GBW f f m         

1 2

1

m m

G G k 

2 2

2

m p L

G f C     

1 2 2 m L L p m M M

G C C GBW f G C kC   

Analog Integrated Circuits – Fundamental building blocks – Basic OTA/Opamp architectures 21

 

2 2

1 , , tan 90 arctan

p zp p

GBW m f GBW f f m f k

 

                 1 tan 90 arctan

L M

C C k m k



               

The two stage opamp design algorithm

5 M

I SR C 

 Step 2 → calculate the differential stage bias current for a given SR and CM

5 M

I SR C  

 Step 3 → calculate the transconductances Gm1 and Gm2

1

2

m M

G GBW C  

1

2

m M

G GBW C    

2 1 m m

G k G  

 Step 4 → find VDSat and the geometry of the input transistors

2I I I W  

Analog Integrated Circuits – Fundamental building blocks – Basic OTA/Opamp architectures 22 1,2 5 1 1 1,2 1,2

2 D

m m DSat DSat

I I G g V V   

5 1,2 1 DSat m

I V G 

1,2

W L      

 Step 5 → choose VDSat for M3, M4 and M5

3,4 5

; W W L L            

The two stage opamp design algorithm

6 7 2 6 6

2 2

D m DSat DSat

I I G V V  

 Step 6 → balance the M3-M4 current mirror by choosing VDSat3=VDSat4=VDSat6 and find the geometry of M6

7 2 6

1 2

m DSat

I G V   

6

W L      

6 6 DSat DSat

 Step 7 → choose VDSat7=VDSat5 and determine the geometry of M7

6

 

7

W L      

Further ideas:  remember the body effect and the parasitic capacitances → Gm-s will always be smaller than expected while capacitances will always be larger → oversize

Analog Integrated Circuits – Fundamental building blocks – Basic OTA/Opamp architectures 23

smaller than expected while capacitances will always be larger → oversize  try to set all currents to be integer multiples of a given bias current  use a current mirror based biasing scheme instead of voltages  iteratively simulate and optimize the design until all specifications have been met

The folded cascode opamp

Analog Integrated Circuits – Fundamental building blocks – Basic OTA/Opamp architectures 24

The folded cascode opamp

 another typical opamp architecture → a differential amplifier followed by a current buffer and a cascode output stage for large Rout  an additional output voltage follower may be used if the load is not strictly capacitive  no need for frequency compensation (more on this later)  no need for frequency compensation (more on this later)  elementary amplifier stages → a single V-I and I-V conversion pair

I-V

Analog Integrated Circuits – Fundamental building blocks – Basic OTA/Opamp architectures 25

cascade of elementary stages (transconductance, common gate and transimpedance) V-I I-V I-I

The folded cascode opamp

 the small signal low frequency model with two equivalent stages  no capacitive effects → low frequency or DC voltage gain  the current buffer → a subsequent I-V and V-I conversion pair with Rp and Gmp adjusted to provide a unity current gain to provide a unity current gain

 

1 p

V

2 p

V

Analog Integrated Circuits – Fundamental building blocks – Basic OTA/Opamp architectures 26

   

1,2 6,7 9 9 11 7 7 5

1 1 ||

m m p mp m

• ut

m DS DS m DS DS

G g R G g R g r r g r r           

m

• ut

a G R 

The folded cascode opamp

 the small signal high frequency model → consider the load and the dominant parasitic capacitances

1 2 1 4 4 6 6 1 2

2 2

p p DB DB GD SB GS p p p

C C C C C C C C C C              2 2

p

C    

 



( ) 1 1

• ut

L p p

a a s sR C sR C   

Since Rout>>Rp and CL>>Cp, the poles are always separated and the phase margin will be typically large (mφ>70°), even if mirror singularities are considered

Analog Integrated Circuits – Fundamental building blocks – Basic OTA/Opamp architectures 27

No need for frequency compensation → the circuit typically works at larger frequencies than the stable two stage opamp

The folded cascode opamp – frequency response

One dominant pole and one high frequency pole (mirror singularities neglected):

1( ) 2

1 2 1 2 2

m

• ut

p d

• ut

L mp p p p p

a G R f R C G f R C C                

Analog Integrated Circuits – Fundamental building blocks – Basic OTA/Opamp architectures 28 1( )

2

m p d L

G GBW a f C    

2

90 arctan

p

GBW m f



         

The folded cascode opamp – step response

V SR t   

 assume unity gain negative feedback and apply an input step to the follower  step response calculated as  Slew Rate (SR) → variation rate of the output voltage

1

( ) ( )

• ut

A s V t s

 

      L

t 

 large phase margin → no overshoot

Analog Integrated Circuits – Fundamental building blocks – Basic OTA/Opamp architectures 29

The folded cascode opamp – slew rate

 the total capacitance of every node must be charged and discharged in each cycle  charging rate depends on the largest current supplied to the node capacitances  the folding node is charged rapidly → SR limited by the output node

B L

I SR C 

Analog Integrated Circuits – Fundamental building blocks – Basic OTA/Opamp architectures 30

The folded cascode opamp design algorithm

1

2

m L

G GBW C  

 Step 1 → calculate the required input stage transconductance

1 1,2

2

m m L

G g GBW C     

 Step 2 → calculate the required input stage bias current

3 B L L

I I SR C C  

3 L

I SR C  

 Step 3 → calculate the VDSat1,2 voltage and the differential transistor pair geometry

2I I  

Analog Integrated Circuits – Fundamental building blocks – Basic OTA/Opamp architectures 31 1,2 3 1,2 1,2 1,2

2 D

m DSat DSat

I I g V V  

1,2 1,2 3 DSat m

V g I  

1,2

W L      

 Step 4 → choose VDSat3 and calculate the geometry of M3

3

W L      

The folded cascode opamp design algorithm

 

6,7 1,2

1.5....2

D D

I I  

 Step 5 → choose ID6,7=ID8,9=ID10,11=(1.5....2)·ID1,2 to avoid completely turning off the cascode stage when the opamp is slew rate limited (all I3 flows through M1 or M2)

 

4,5 1,2 6,7 1,2

2.5....3

D D D D

I I I I    

 Step 7 → choose VDSat for all transistors (except M1, M2 and M3) and determine the geometries Further ideas:  remember the body effect and the parasitic capacitances → Gm-s will always be smaller than expected while capacitances will always be larger → oversize

Analog Integrated Circuits – Fundamental building blocks – Basic OTA/Opamp architectures 32

smaller than expected while capacitances will always be larger → oversize  try to set all currents to be integer multiples of a given bias current  use a current mirror based biasing scheme instead of voltages  iteratively simulate and optimize the design until all specifications have been met

Bibliography

 P.E. Allen, D.R. Holberg, CMOS Analog Circuit Design, Oxford University Press, 2002  B. Razavi, Design of Analog CMOS Integrated Circuits, McGraw-Hill, 2002  D. Johns, K. Martin, Analog Integrated Circuit Design, Wiley, 1996  P.R.Gray, P.J.Hurst, S.H.Lewis, R.G, Meyer, Analysis and Design of Analog Integrated Circuits, Wiley,2009  R.J. Baker, CMOS Circuit Design, Layout and Simulation, 3rd edition, IEEE Press, 2010

Analog Integrated Circuits – Fundamental building blocks – Basic OTA/Opamp architectures 33