Digitally Assisted Analog Circuits Boris Murmann Stanford - - PowerPoint PPT Presentation

Digitally Assisted Analog Circuits

Boris Murmann Stanford University Department of Electrical Engineering murmann@stanford.edu

Digitally Assisted Analog Circuits

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Outline

• Motivation

– Progress in digital circuits has outpaced performance growth in analog circuits by a large margin

• Digitally Assisted A/D Converters

– Using digital computing capabilities as a new driver to improve A/D converter energy efficiency – Examples

• Experimental proof-of-concept result
• Next generation designs
• Conclusions

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Modern Electronic Circuits

• Trend towards ubiquitous sensing, communication

and computing

– "Ambient Intelligence"

• Signal processing predominantly done in digital

domain

– Rapidly improving digital capabilities, fueled by "Moore's Law"

• Irreplaceable "bottleneck" - analog circuits

– Analog-Digital Converters (ADCs) – Digital-Analog Converters (DACs) – Filters and amplifiers (Anti-aliasing, RF power amplification, …)

• Focus of this talk: ADCs

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Issue 1: Throughput

150x 15 years

1 10 100 1000 10000 1987 1995 2003 Relative Performance

ADC* (2x / 4.7 years) µP MIPS (2x / 1.5 years)

* Performance measure: Bandwidth x Number of quantization levels

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Issue 2: Power and Energy

• Example: Cell phone

– Battery has roughly 3Wh of Energy – For a talk time of 12 hours, can draw no more than 250mW – Only a fraction of that power available for ADC

• In an increasing number of applications, key issue is

how much performance you can squeeze into a fraction of 0.1…1Watt

• What is the trend in ADC versus digital power/energy

consumption?

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ADC Energy versus Digital Energy

• Interesting metric to look at

– How many digital gates can you toggle for the energy needed in

• ne A/D conversion?
• Example

– Standard digital gates (NAND2) in 0.13mm CMOS consume about 6nW/Gate/MHz

• Energy/Gate = 6fJ

– State-of-the-art 10-bit ADC consumes 1mW/MSample/sec

• Energy/Conversion = 1nJ

– Energy equivalent number of gates

• 1nJ/6fJ= 166,666

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Impact of Technology Scaling

100,000 200,000 300,000 400,000 500,000 0.0 0.2 0.4 0.6 0.8 Feature Size [ µm] Energy Equivalent # of Gates 6bits 8bits 10bits 12bits 14bits 16bits ADC Resolution:

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Observations

• Energy equivalent number of gates per A/D

conversion has gone through the roof

• Reason

– Digital circuits have scaled well with technology – Analog doesn't benefit quite as much from smaller features

• Issues: Low supply voltage, low device gain, …
• Key idea

– Build "digitally assisted analog circuits" – Find a way to leverage digital processing capabilities to improve performance and lower power of analog circuits

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Analog Circuit Challenges

Power Dissipation Speed Matching Linearity Noise Precision

Matching and linearity constraints are not fundamental

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A New Generation of ADCs

• Conventional ADC

– Precisely linear mapping from input to

• utput

– Relies on highly linear and well matched analog components

• Digitally assisted

ADC

– A "sloppy" one-to-one mapper – Digital postprocessor estimates ADC errors and applies corrections

Low Complexity “Sloppy” ADC Vin Daccurate Dsloppy Digital Postprocessor Vin Daccurate “Accurate” ADC

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Examples

• Digitally assisted pipeline ADC

– Murmann & Boser, ISSCC 2003

• Minimum complexity, ultra low energy pipeline ADC

– Under development in my research group

• ADC with embedded calibration for OFDM systems

– Under development in my research group

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Pipeline ADC

• Bottleneck: Highly linear gain element
• A/D

D/A

• D

Vres Vin STAGE 1 STAGE N-1 STAGE N S/H R bits Vin 2R D=0 D=1

• V

res

Vin (e.g. R=1)

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Open-Loop Gain Element

+ Lower Noise + Increased Signal Range + Lower Power + Faster – Nonlinear

• Use DSP to

linearize!

Open-Loop Amplifier Conventional Precision Amplifier

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Digital Nonlinearity Correction

System ID

Analog Nonlinearity Digital Inverse Modulation Dout,corr Vin Dout Parameters

• Use digital system identification techniques to determine
• ptimum post distortion function
• Possible (and often necessary) to track correction parameters

without interrupting normal ADC operation

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Experimental Verification

• 12bit, 75MSamples/sec, 0.35µm, post-processor off chip
• Based on commercial part (Analog Devices AD9235)

REFERENCE AND BIAS PIPELINE BACKEND STAGE1 SHA CLK LOGIC

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Block Diagram

• Proof of concept design

– Open-loop amplifier only in first, most critical stage

• Judicious analog/digital co-design

– Only two corretion parameters (linear and cubic amplifier error)

~8400 Gates (0.042mm2 in 0.13µm)

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Linearity Improvement

1000 2000 3000 4000

• 20
• 10

10 20 Post-Proc. OFF Post-Proc. ON

Code

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Amplifier Power

10 20 30 40 50 60 Power [mW]

• 62% (33mW)

Commercial Part (Precision Amplifier) This Work (Simple Amplifier)

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Digital Post-Processor

Area=1.4mm2 (18%) Power=10.5mW (3.6%)

• 8400 Gates, 64 bytes RAM, 64kBit ROM
• Place & Route in 0.35µm technology

Pipelined ADC (7.9 mm2)

Post-Processor

10 20 30 40 Amplifier Savings Post- Processor Power [mW]

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Going Beyond a Proof of Concept

• Proof-of-concept design showed that the

idea of digital assistance works, but power savings were not "revolutionary"

• As a more aggressive step, it is now

interesting to explore the question: How many "analog" transistors do we really need?

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Minimalistic Pipeline ADC Stage

• Use a single active device, operated like a charge

pump to implement gain element

• Highly energy efficient, low noise, …
• Gain is imprecise and nonlinear, but post-processor

can take care of that

Vin

• ✷
• ✶
• ✷

CL (next stage) Vres 1 1 1 2 CDAC VDAC VREFN,P

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Simulated Energy/Conversion

• 9-bit, "minimalistic" pipeline ADC prototype in 90nm technology

– Roughly 20,000 gates used for digital post-processing – Only 7pJ per conversion, ~50x below state-of the art

1.E+00 1.E+01 1.E+02 1.E+03 1.E+04 1.E+05 1.E+06 30 40 50 60 70 80 90 100 110 SN(D)R [dB] Energy/Conversion [pJ] Minimalistic Pipeline I SSCC 1998-2005

• Expon. (I

SSCC 1998-2005)

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Attributes (1)

• At 10MSamples/s (~video-rate), this ADC consumes
• nly 70µW
• Can be powered from a 1cm3 size battery for more

than 1 year!

– A state-of the art ADC will drain the battery within a few days…

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Attributes (2)

• Energy/conversion is dominated by digital post-

processing

• Great news!

– Energy efficiency will improve further when design is scaled to 65nm, 45nm, …

29

An

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The Calibration Problem

• The "sloppier" we make the analog portion of the

ADC, the more parameters we need to estimate and track

– Can become quite complex or even impossible without disturbing normal ADC operation

• Idea: "System Embedded" postprocessing and

calibration of ADC

– Leverage redundancy and knowledge of certain input signal properties to estimate ADC errors – Re-use existing system resources for ADC calibration

• Example: ADC for OFDM receivers

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Embedded ADC Calibration for OFDM

• Communications protocol uses "pilot tones" to

measure and equalize RF channel nonidealities

• Why not use these pilots to "equalize" ADC?

– Errors in pilot signals can be used to estimate correction parameters for sloppy ADC

IFFT

DAC

FFT

f pilot f pilot ADC

Channel

DSP error

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Typical Learning Curve

~100ms

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Conclusions (1)

• Analog circuit improvements lag progress of digital

functions

– Technology scaling only conditionally benefits analog circuit performance

• Digitally assisted analog circuits offload accuracy

constraints to digital processor

• ADCs are obvious candidates for "digital assistance"

– The benefits of digital pre/postprocessing are also being investigated for several other analog circuit blocks

• Signal pre-distortion in RF power amplifiers
• Signal pre-distortion in DACs
• High-speed wireline interfaces

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Conclusions (2)

• Key benefits

– Lower power and potentially higher speed

• Up to 100x reduction in ADC energy/conversion

– Digitally assisted ADCs will benefit from future technology scaling

• "Sloppy" circuits will be compatible with low voltage, low gain,

ultimately scaled CMOS

• Key challenges

– Interdisciplinary nature of design problem

• Device modeling, circuit design
• Math, signal processing algorithms
• Inclusion of application layer

– Design complexity and turnaround time