[PPT] - Analog Integrated Circuits Fundamental Building Blocks Fundamental PowerPoint Presentation

SLIDE 1

Analog Integrated Circuits Fundamental Building Blocks

Faculty of Electronics Telecommunications and Information Technology

Fundamental Building Blocks

Current and voltage references

Information Technology

Gabor Csipkes

Bases of Electronics Department

SLIDE 2

Outline

 references as independent sources, parameters  simple dividers as voltage reference  MOS or bipolar diode voltage references  MOS or bipolar diode voltage references  a Zener diode voltage reference  self biased current references (self biased current mirrors)  bipolar and MOS Widlar current references (PTAT)  VTh and VBE references (CTAT)

Analog Integrated Circuits – Fundamental building blocks – Current and voltage references 2

 bootstrapping and supply voltage independence  bandgap references

SLIDE 3

References - definitions

 current and voltage references → active implementations of independent sources  the output current or voltage is independent on load, temperature and supply voltage  reference → better precision, sensitivity and temperature coefficient than average circuitry → closer to ideal sources circuitry → closer to ideal sources Sensitivity = the relative variation

f the output voltage or current Xref

with respect to the parameter y

ref y Xref ref

X y S y X     1

ref ref

X TC T X    

Temperature coefficient = the temperature sensitivity of the output voltage or current Xref, normalized to 1°

Analog Integrated Circuits – Fundamental building blocks – Current and voltage references 3

 references often exploit

physical dependences in integrated components (e.g. temperature dependence of a

junction voltage or the thermal voltage)

advantages rising from circuit topologies (e.g. resistor ratio independent on

temperature)

SLIDE 4

A voltage divider as reference

2 1 2 ref DD

R V V R R   

2 1 2

1

DD

ref V DD DD

V V R V R R S       

Passive: passive active

2 1 2 1 2 2

1

DD ref

ref V DD DD V DD ref DD

V R V R R S V V R R R V        

→ a 1% variation of VDD produces 1% variation

f the reference voltage

 

2 1 1 D n GS Thn

I V V     

Active:

1 2 D D

I I 

| | 1

DD Thn Thp ref Thn n

V V V V V      

Analog Integrated Circuits – Fundamental building blocks – Current and voltage references 4

 

1 1 2 2 2 2 1 1 2

| | ; 2 2

D n GS Thn D p SG Thp p

x

n

x

n p

I V V I V V C W C W L L                  

| |

DD ref

ref V DD DD V DD ref n DD Thn Thp p

V V V S V V V V V         

1

n p

 

1 

SLIDE 5

A bipolar or MOS diode voltage reference

DD ref ref Th

V V V V R    

MOS:

 

2

DD ref

ref V DD DD V DD ref ref DD ref

V V V S V V V R V V       

ln

CC ref ref T

V V V V      

Bipolar:

 

1 , , ,

ref Vref VDD VCC VTh R ref

V TC f TC TC TC TC T V

 

    

 non-linear variation of Vref with I → the

Analog Integrated Circuits – Fundamental building blocks – Current and voltage references 5

ln

ref T S

V V RI     

 

DD ref

ref V CC CC T V CC ref ref CC ref

V V V V S V V V V V       

 non-linear variation of Vref with I → the sensitivity decreases with Vref  non-linearity more effective for bipolar transistors (exponential vs. quadratic)  Vref range relatively low (VBE or VGS)

SLIDE 6

A bipolar or MOS diode voltage reference

1

DD ref ref Th

V V R V V R R                 

MOS:  extending the output voltage range with an additional voltage divider

2 ref Th

R R       

 

2

DD ref

ref V DD DD V DD ref ref DD ref

V V V S V V V R V V       

Bipolar:

 

1 , , ,

ref Vref VDD VCC VTh R

V TC f TC TC TC TC T V

 

    

Analog Integrated Circuits – Fundamental building blocks – Current and voltage references 6 1 2

1 ln

CC ref ref T S

V V R V V R RI               

 

DD ref

ref V CC CC T V CC ref ref CC ref

V V V V S V V V V V       

 

Vref VDD VCC VTh R ref

T V

 



 the reference voltage still depends on all the temperature sensitive components

SLIDE 7

A Zener diode voltage reference

 the Zener effect → avalanche breakdown of a pn junction under the effect of a large enough reverse biasing  the large intrinsic electric field created by the wide depletion region breaks minority carrier bonds → voltage drop relatively constant and well defined with changing current  abrupt current to voltage dependence of the diode decreases supply sensitivity reverse junction current abrupt breakdown VBV=ct.  supply voltages often 1.2V-1.5V  typical VBV in CMOS larger than 4-5V

Analog Integrated Circuits – Fundamental building blocks – Current and voltage references 7

reverse junction voltage  drawback → relatively large VBV → inappropriate for low voltage applications

SLIDE 8

Self biased current mirror reference

 uses Vref of the diode voltage reference to control a current source

V V



 if the transistors are matched and balanced in voltage → supply voltage sensitivity inherited from Iref

DD DD

ut

ref

V V I I

S S 

Analog Integrated Circuits – Fundamental building blocks – Current and voltage references 8

ref

 possible improvement → scale the Iref sensitivity with a coeffcient smaller than unity  partly linear transformation of Vref into Iout → Widlar current reference (mirror)

; 1

DD DD

ut

ref

V V I I

S k S k   

SLIDE 9

Widlar current references

 MOS and bipolar implementations are possible

1 2 2 1 GS GS

ut

ref GS Th

V V I R I V V         

1 2 2 1

ln

BE BE

ut

ref BE T

V V I R I V V I           

1 1 2 2 GS Th

ut

GS Th

V V I V V            

1 1 2 2

ln ln

BE T S

ut

BE T S

V V I I V V I                  

2

1 1 1 4

ref

ut

I I R             

2

ln

ref S T

ut

I I V I R I I      

Analog Integrated Circuits – Fundamental building blocks – Current and voltage references 9 2 2 2 1 2

4 2

ut

I R R             

2 1

ln

ut
ut

S

I R I I      

1 1 2 1

2

DD DD

ut

ref

V V DSat I I DSat DSat

V S S V V



      

2 1

DD DD

ut

ref

V V T I I T

ut

V S S V R I



      

SLIDE 10

VTh and VBE current references

 similar to Widlar references but voltage to current conversion entirely linear

1 ref Th GS

ut MOS

I V V I R R 



  

1 1 2 2

ln

ref T S BE

ut BJT

I V I V I R R



       

2 2

ut MOS

R R



 increased output resistance due to the cascode effect of M2 and Q2

Analog Integrated Circuits – Fundamental building blocks – Current and voltage references 10

 

1 1

MOS: 2

DD DD

ut

ref

V V DSat I I DSat Th

V S S V V   

1

Bipolar:

DD DD

ut

ref

V V T I I BE

V S S V  

 lowest possible supply voltage sensitivity among self biased references

SLIDE 11

Supply independent references - principle

 self biasing ties the output voltage or current to VDD-VCC → inherent supply sensitivity  idea: define Iref as function of Iout → supply in dependence in any Widlar, VTh or VBE reference  implies a positive feedback loop and the double definition of Iout → bootstrapping implies a positive feedback loop and the double definition of Iout → bootstrapping What is this ??

ref

I

ut

I

Analog Integrated Circuits – Fundamental building blocks – Current and voltage references 11

SLIDE 12

Bootstrapped current references – startup

 stable operating point → Iref=Iout  positive feedback loop → two stable operating points, one at the origin (Iref=Iout=0)  the startup circuit prevents the loop to settle in the origin and is deactivated once it starts to converge to the desired operating point starts to converge to the desired operating point

ref

I

ut

I

Analog Integrated Circuits – Fundamental building blocks – Current and voltage references 12

 Iref=Iout=0 → VGS1=0 → VGS7 >> → M7 pumps current into M1 → Iout and Iref rise  when Iref and Iout are large enough, VGS1 increases pushing VGS7 to 0 and the startup circuit is disabled (ID7=0)

SLIDE 13

Bootstrapped current references

 the theoretical sensitivity of Iout with VDD is zero if Iout=Iref  in practice, the M3-M4 mirror is unbalanced → ΔV

3 4

( , )

ut

in SD SD

V V V V V V V V f I V           V 

3 1 4 4

( , ) ( )

SD DD GS ref DD SD SG

ut

V V V f I V V V f I         

1 4 DD GS SG

V V V V     ( )

ref V

I n f V S    

Analog Integrated Circuits – Fundamental building blocks – Current and voltage references 13

 the sensitivity can be decreased by using a cascode or balanced Wilson mirror  the expression of the output current depends on the core reference (Widlar, VTh, VBE)

( )

DD

ut

ref V DD I

ut

I n f V S I    

SLIDE 14

Temperature compensated references

 idea: take two voltages with complementary TC and calculate weighted sum to obtain temperature independence Two voltage types are typically used: VBE and ΔVBE PTAT CTAT  variation of ΔVBE with temperature

I    I I kT  

Analog Integrated Circuits – Fundamental building blocks – Current and voltage references 14

1 1 1 2 2 2

ln ln

C BE T S C BE T S

I V V I I V V I                     

1 2 1 2 2 1 ( )

ln

C S BE BE BE T C S f T

I I kT V V V V q I I 



            

PTAT=Proportional To Absolute Temperature

 

0.085mV/

BE T

V V C T T            

SLIDE 15

Temperature compensated references

 variation of VBE with temperature → recall the bipolar transistor saturation current

/ / / 2 / E n p p n E S B n A D B p i

qA D n q n A D I W N W  

temperature dependent terms

a – constant (2.4 for electrons and 2.2 for holes in

/ / 2 3

G

a n p n p qV kT i

kT kT D C T q q n DT e 

 

            

a – constant (2.4 for electrons and 2.2 for holes in

silicon)

VG0 – silicon band gap extrapolated to 0K (1.205V)
C, D – temperature independent, material and

technology specific constants

1 3 4

G G

qV qV a a E kT kT S

kA CD I T T e bT e N W

   

         

4

ln

a C BE G

I kT V V T q b



        

Analog Integrated Circuits – Fundamental building blocks – Current and voltage references 15

CTAT=Complementary To Absolute Temperature

/ S A D B b

N W     

BE G

q b    

 

4

BE G BE

V V V a k T T q       2mV/

BE

V C T    

SLIDE 16

Bandgap references – principle

 generate a VBE voltage by forcing a current through a bipolar diode  obtain a ΔVBE voltage by using an appropriate voltage loop in a PTAT circuit → typically some form of the bipolar Widlar current mirror  weight the thermal voltage VT and sum with VBE → α must be temperature independent

T BE

ut

BE T

V V V   

ut

BE T

V V V T T T           

BE T

V V T T         2mV / 23.5 0.085mV / C C     

Analog Integrated Circuits – Fundamental building blocks – Current and voltage references 16

 real VBE exhibits curvature → does not decrease linearly with T → the compensation is not perfect  designs usually optimized for nominal operating temperature where TC=0  the output voltage is around 1.2V → bandgap

SLIDE 17

Bandgap references – examples

1 1 1 3 2 2

ut

BE BE

V V I R V I R    

Widlar bandgap reference → bipolar technology Kirchhoff’s voltage law (KVL) for V

ut :

1 1 1 3 2 2

ut

BE BE

V V I R V I R    

Widlar current mirror:

1 2 1 2 2 3 2 3 2 3 1

ln ln

T T BE BE

V I V R V V I R I R I R R                 

2 1 2 3 1 3 1 2 1 S S S BE BE

R I I I V V I I R       

Analog Integrated Circuits – Fundamental building blocks – Current and voltage references 17

ut

BE T

V V V   

2 2 1 3 1

ln

ut

BE T

R R V V V R R         

2 2 3 1

ln ( ) R R f T R R         

SLIDE 18

Bandgap references – examples

1 2 2 1 BE BE

V V I R  

Song bandgap reference → BiCMOS or CMOS technology with lateral PNP transistors Widlar current mirror:

1 2 2 1 BE BE 2 1 2 1 2 1

ln

S T PTAT S

I V I I I R I I         

2 2 1 1 S E S E

I A N I A  

KVL for V :

Analog Integrated Circuits – Fundamental building blocks – Current and voltage references 18

ut

BE T

V V V   

2 3 1

ln

ut

BE T

R V V V N R   

2 1

ln ( ) R N f T R   

KVL for V

ut :

3 2

ut

BE PTAT

V V I R  

SLIDE 19

Bandgap references – examples

Brokaw bandgap reference Widlar current mirror:

1 2 2 2 BE BE

V V I R   I V I  

2 1 2 2 2 1

ln

S T S

I V I I R I I        

2 2 1 1 S E S E

I A N I A  

KVL for V

ut :

V V

 



Analog Integrated Circuits – Fundamental building blocks – Current and voltage references 19

ut

BE T

V V V   

1 1 2

2 ln

ut

BE T

R V V V N R   

 

1 1 1 2

ut

BE

V V R I I   

1 2

2 ln ( ) R N f T R   

SLIDE 20

Bandgap references – examples

BiCMOS bandgap reference Widlar current mirror:

1 2 3 1 BE BE

V V I R  

2 1 3 1 3 1

ln

S T S

I V I I R I I        

2 2 1 1 S E S E

I A N I A  

KVL for V

ut :

 

4 2 3 5

ut

BE

V V R I I    I I I I   

Analog Integrated Circuits – Fundamental building blocks – Current and voltage references 20

ut

BE T

V V V   

2 4 1

2 ln

ut

BE T

R V V V N R   

2 1

2 ln ( ) R N f T R   

1 2 3 5

I I I I   

SLIDE 21

Bandgap references – examples

CMOS sub-bandgap reference with lateral PNP transistors Widlar current mirror:

1 2 2 1 EB EB

V V I R  

 



2 1 2 1 2 1

ln

S T S

I V I I R I I        

2 2 1 1 S E S E

I A N I A  

KCL at the output node :

V V

 



V V R

KVL for V

ut :

Analog Integrated Circuits – Fundamental building blocks – Current and voltage references 21

 

ut

BE T

V V V    

     

3 4 5 2 3 3 4 5 2 3 5 1 ( ) ( )

ln

ut

EB T f T f T

R R R R V V V N R R R R R R R

   

                       

3 3 2

ut

EB

V V I R  

 

5 3 2 4 5 2 4 5 3 4 5

ut
ut

V V R I I I I I R R R R R        

SLIDE 22

Bandgap references – examples

Bipolar sub-bandgap reference Widlar current mirror:

1 2 2 2 BE BE

V V I R   I V I   I A

V V

 



2 1 2 2 2 1

ln

S T S

I V I I R I I        

2 2 1 1 S E S E

I A N I A  

V V

 



 

1 1 1 2 3

ut

BE

V V R I I I    

KVL for V

ut :

 

7

ut

V R I 

Analog Integrated Circuits – Fundamental building blocks – Current and voltage references 22

Brokaw cell

 

ut

BE T

V V V    

   

5 6 7 1 1 5 6 7 1 7 2 ( ) ( )

2 ln

ut

BE T f T f T

R R R R V V V N R R R R R R

   

                      

 

7 3 5 6 7

ut

I R R R  

SLIDE 23

Bibliography

 P.E. Allen, D.R. Holberg, CMOS Analog Circuit Design, Oxford University Press, 2002  B. Razavi, Design of Analog CMOS Integrated Circuits, McGraw-Hill, 2002  D. Johns, K. Martin, Analog Integrated Circuit Design, Wiley, 1996  P.R.Gray, P.J.Hurst, S.H.Lewis, R.G, Meyer, Analysis and Design of Analog Integrated Circuits, Wiley,2009  R.J. Baker, CMOS Circuit Design, Layout and Simulation, 3rd edition, IEEE Press, 2010

Analog Integrated Circuits – Fundamental building blocks – Current and voltage references 23