A 74.9 dB SNDR 1 MHz Bandwidth 0.9 mW Delta-Sigma Time-to-Digital - PowerPoint PPT Presentation

A 74.9 dB SNDR 1 MHz Bandwidth 0.9 mW Delta-Sigma Time-to-Digital Converter Using Charge Pump and SAR ADC Anugerah Firdauzi, Zule Xu, Masaya Miyahara, and Akira Matsuzawa Tokyo Institute of Technology, Japan

Outline 2 • Introduction • Circuit design – Charge-pump – Time-domain feedback – SAR ADC as quantizer • Performance summary • Conclusion IEEE ISCAS 2016 A 74.9 dB SNDR 1 MHz Bandwidth 0.9 mW Delta-Sigma Time-to-Digital Converter Using Charge Pump and SAR ADC

Time to Digital Converter 3 • Measuring time difference between electrical events Particle detector in Positron Emission Tomography High Energy Physics γ -detector Absorber Emitter TDC T 1 + T 2 γ TDC Laser range finder All Digital PLL T 1 F ref Laser F out Phase Digital Detector Filter Object TDC DCO TDC Counter Detector T 2 IEEE ISCAS 2016 A 74.9 dB SNDR 1 MHz Bandwidth 0.9 mW Delta-Sigma Time-to-Digital Converter Using Charge Pump and SAR ADC

TDC Prior Arts 4 • Flash / delay-line • Pipeline  Simple  High resolution  Technology-limited resolution  Require a linear time amplifier  Inter-stage mismatch CK 1 t d t d t d Fine Coarse CK 1 Delay Delay CK 2 TA CK 2 line line D out D out Thermal to binary encoder Logic [R. Staszewski , RFIC ‘04] [M. Lee, VLSIC ‘07] IEEE ISCAS 2016 A 74.9 dB SNDR 1 MHz Bandwidth 0.9 mW Delta-Sigma Time-to-Digital Converter Using Charge Pump and SAR ADC

ΔΣ TDC Prior Arts 5 • Gated Ring Oscillator • Switched Ring Oscillator  Breaking the technology-  No dead-zone issue limited resolution  Always running VCO → high  Dead-zone issue power V H V L T in GRO SRO T in Clr Clr Differentiator Differentiator Out Out [M.Z. Straayer , JSSC ‘09] [A. Elshazly , JSSC ‘14] IEEE ISCAS 2016 A 74.9 dB SNDR 1 MHz Bandwidth 0.9 mW Delta-Sigma Time-to-Digital Converter Using Charge Pump and SAR ADC

Voltage-domain TDC 6 • Time-to-voltage followed by analog-to-digital conversion  More relaxed technology-constrained resolution  High resolution ADC is required • Typical implementation UP o Charge-pump + SAR ADC CK 1 CLR D out [Z. Xu , CICC ‘13] PFD ADC DN o Charge-pump + ΔΣ ADC C CK 2 [M.B. Dayanik , ESSCIRC ‘15] IEEE ISCAS 2016 A 74.9 dB SNDR 1 MHz Bandwidth 0.9 mW Delta-Sigma Time-to-Digital Converter Using Charge Pump and SAR ADC

Mixed-domain ΔΣ TDC 7 • Gm-cell as integrator + time-domain feedback  Simplified ADC design  Power-starving integrator  Only for positive input T in Σ D out Counter Gm ADC T dtc C T dtc Ф fast DTC [M. Gande , VLSIC ‘12] IEEE ISCAS 2016 A 74.9 dB SNDR 1 MHz Bandwidth 0.9 mW Delta-Sigma Time-to-Digital Converter Using Charge Pump and SAR ADC

Proposed Mixed-domain ΔΣ TDC 8 • Integrator implementation by charge preservation TVC and Σ Δ  Compact design Low-  Low power resolution UP ADC  Differential input CK 1 Time PFD ADC D out sub DN C CK 2 DTC IEEE ISCAS 2016 A 74.9 dB SNDR 1 MHz Bandwidth 0.9 mW Delta-Sigma Time-to-Digital Converter Using Charge Pump and SAR ADC

Charge-pump as Integrator 9 • Bottom-plate sampling – Reduces charge injection – Prevents charge- pump’s current mismatch C CK 1 I CP C CK 2 UP D Q U UP R D DN CK 1 S 1 V o T d T in V V o CK 2 C int Δ Δ V o R T d S 2 D Q S S 1 DN S S 2 I CP 𝜠𝑾 𝒑 = 𝑱 𝐃𝐐 . 𝑼 𝐣𝐨 /𝑫 𝐣𝐨𝐮 sampling sampling conversion IEEE ISCAS 2016 A 74.9 dB SNDR 1 MHz Bandwidth 0.9 mW Delta-Sigma Time-to-Digital Converter Using Charge Pump and SAR ADC

Charge-sharing Phenomenon 10 • 1. Before sampling 2. Sampling 3. Sampling finish Op-amp can reduce charge- I CP I CP sharing before and spilled charge after sampling C PP C PP V O - Δ V O V O V O V DD /2 V DD /2 V DD /2 C int C int C int 1 2 3 spilled charge C PN C PN CK 1 CK 2 equal I CP I CP I CP charge UP C PP C PP DN V O V O ’ V O + + + V M V M V M - C int - C int - C int V O equal charge I CP I CP I CP C PN C PN IEEE ISCAS 2016 A 74.9 dB SNDR 1 MHz Bandwidth 0.9 mW Delta-Sigma Time-to-Digital Converter Using Charge Pump and SAR ADC

Pseudo Diff. Charge-pump 11 • Op-amps provide an Ф 2 CMFB Ф 1 V BP,CMFB isolated CMFB voltage V BP from the actual C CM2 V CP C CM1 sampled voltage V CM V CUP V CUN Ф 1 Ф 2 UP DN DN UP R M R M V OP V ON V M R M R M V MP V MN + + + + V OP V ON - - - - V M C int C int C int C int nt C CM1 DN DN UP V MP V MN UP V CD V CD P N V CN V BN IEEE ISCAS 2016 A 74.9 dB SNDR 1 MHz Bandwidth 0.9 mW Delta-Sigma Time-to-Digital Converter Using Charge Pump and SAR ADC

Time-domain Feedback 12 • Using delay-line Digital-to-Time Converter (DTC) • Input is delayed based on TDC’s output T IN D IN Positive input Negative input CK 1 CK 2 T IN T OUT OUT>0 →delay CK 1 T IN -T OUT>0 … OUT<0 →delay CK 2 T IN -T OUT<0 DTC Time subtraction method IEEE ISCAS 2016 A 74.9 dB SNDR 1 MHz Bandwidth 0.9 mW Delta-Sigma Time-to-Digital Converter Using Charge Pump and SAR ADC

Proposed ΔΣ TDC Architecture 13 TVC and Σ Δ 4-bit SAR ADC D out > 0 CDAC CK 1 0 I CP V dacp UP DN DTC 1 C int - V inp SAR Logic + D out PFD D out < 0 - V inn + DN UP C int CK 2 0 V dacn DTC 1 I CP CDAC z -1 IEEE ISCAS 2016 A 74.9 dB SNDR 1 MHz Bandwidth 0.9 mW Delta-Sigma Time-to-Digital Converter Using Charge Pump and SAR ADC

TDC Noise Analysis 14 • Thermal noise and quantization noise are the dominant noise sources C int = 0.5 pF -80 90 without thermal noise Thermal noise Noise power (dB) dominates C int = 2 pF 85 with -85 1 pF SNDR (dB) thermal 0.5 pF noise 80 0.25 pF -90 Total noise 75 Thermal noise -95 70 Quantization Quantization noise noise dominates -100 65 2 3 4 5 6 7 2 3 4 5 6 7 Quantizer size (bit) Quantizer size (bit) IEEE ISCAS 2016 A 74.9 dB SNDR 1 MHz Bandwidth 0.9 mW Delta-Sigma Time-to-Digital Converter Using Charge Pump and SAR ADC

SAR ADC Quantizer 15 • SAR ADC: low power, low complexity, moderate speed • Separated CDAC and charge-pump capacitor  Reduce disturbance to sampled charge  Smaller CDAC cap for faster conversion V outn + - SAR Logic V outp D out V in + V dac - CK CK 2 N-1 C u … C u C u V inp V dacp V dacn V inn V refn CK V refp CDAC [M. Miyahara, A- SSCC ‘08] IEEE ISCAS 2016 A 74.9 dB SNDR 1 MHz Bandwidth 0.9 mW Delta-Sigma Time-to-Digital Converter Using Charge Pump and SAR ADC

Performance Summary 16 • 830 kHz 2.4ns pp input at 1 MHz bandwidth, 200 MHz sampling freq. 0 80 SNDR = 74.9 dB Normalized PSD (dB) ENOB = 12.1 bit -20 60 SNDR (dB) -40 F BW 40 -60 20 -80 20 dB/dec 0 -100 -80 -60 -40 -20 0 0.1 1 10 100 Input amplitude (dBFS) Frequency (MHz) IEEE ISCAS 2016 A 74.9 dB SNDR 1 MHz Bandwidth 0.9 mW Delta-Sigma Time-to-Digital Converter Using Charge Pump and SAR ADC

Core Layout Implementation 17 142 μ m • Core area: 0.017 mm 2 121 μ m IEEE ISCAS 2016 A 74.9 dB SNDR 1 MHz Bandwidth 0.9 mW Delta-Sigma Time-to-Digital Converter Using Charge Pump and SAR ADC

Performance Comparison 18 JSSC JSSC CICC ESSCIRC VLSIC This* ’09 ‘14 ‘13 ‘15 ‘12 CP+ CP+ CP+ ΔΣ TDC Type GRO SRO GSRO ΔΣ ADC Gm-C SAR 1 st 1 st 2 nd 3 rd 3 rd 1 st Filter order CMOS (nm) 130 90 65 65 130 65 Sampling (MHz) 50 500 400 270 90 200 Bandwidth (MHz) 1.0 1.0 4.0 1.0 2.8 1.0 SNDR (dB) 95.0 63.1 80.4 N/A 67.0 74.9 Integ. noise (fs rms ) 80 315 148 176 866 269 Resolution (ps)** 0.28 1.09 0.51 0.61 3.00 0.63 Power (mW) 21.0 2 6.55 8.4 2.58 0.9 FoM (fJ/conv)*** 227 860 96 N/A 250 99 Area (mm 2 ) 0.04 0.02 0.05 0.055 0.425 0.017 *Transistor-level simulation **Resolution = 12 × integrated noise ***FoM = Power/(2 × bandwidth × 2 (SNDR-1.76)/6.02 ) IEEE ISCAS 2016 A 74.9 dB SNDR 1 MHz Bandwidth 0.9 mW Delta-Sigma Time-to-Digital Converter Using Charge Pump and SAR ADC

Conclusion 19 • A mixed time and voltage domain TDC is proposed • Charge-pump is used both as VTC and integrator to achieve low power performance • The ΔΣ implementation allows a good TDC resolution while only using a low bit SAR ADC as quantizer IEEE ISCAS 2016 A 74.9 dB SNDR 1 MHz Bandwidth 0.9 mW Delta-Sigma Time-to-Digital Converter Using Charge Pump and SAR ADC

Acknowledgement 20 • This work was partially supported by MIC, STARC, HUAWEI, Mentor Graphics for the use of the AFS Platform, and VDEC in collaboration with Cadence Design Systems, Inc. IEEE ISCAS 2016 A 74.9 dB SNDR 1 MHz Bandwidth 0.9 mW Delta-Sigma Time-to-Digital Converter Using Charge Pump and SAR ADC

A 74.9 dB SNDR 1 MHz Bandwidth 0.9 mW Delta-Sigma Time-to-Digital Converter Using Charge Pump and SAR ADC Anugerah Firdauzi, Zule Xu, Masaya Miyahara, and Akira Matsuzawa firdaus@ssc.pe.titech.ac.jp