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A 74.9 dB SNDR 1 MHz Bandwidth 0.9 mW Delta-Sigma Time-to-Digital Converter Using Charge Pump and SAR ADC Anugerah Firdauzi, Zule Xu, Masaya Miyahara, and Akira Matsuzawa Tokyo Institute of Technology, Japan Outline 2 Introduction

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A 74.9 dB SNDR 1 MHz Bandwidth 0.9 mW Delta-Sigma Time-to-Digital Converter Using Charge Pump and SAR ADC

Anugerah Firdauzi, Zule Xu, Masaya Miyahara, and Akira Matsuzawa

Tokyo Institute of Technology, Japan

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IEEE ISCAS 2016

Outline

  • Introduction
  • Circuit design

– Charge-pump – Time-domain feedback – SAR ADC as quantizer

  • Performance summary
  • Conclusion

A 74.9 dB SNDR 1 MHz Bandwidth 0.9 mW Delta-Sigma Time-to-Digital Converter Using Charge Pump and SAR ADC

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Time to Digital Converter

  • Measuring time difference between electrical events

A 74.9 dB SNDR 1 MHz Bandwidth 0.9 mW Delta-Sigma Time-to-Digital Converter Using Charge Pump and SAR ADC

Emitter Absorber

+

Particle detector in High Energy Physics Positron Emission Tomography Laser Detector Object Laser range finder Phase Detector Digital Filter Counter Fref Fout DCO All Digital PLL T2 T1 T1 T2 γ TDC γ-detector TDC TDC TDC

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TDC Prior Arts

  • Flash / delay-line

 Simple  Technology-limited resolution

  • Pipeline

 High resolution  Require a linear time amplifier  Inter-stage mismatch

A 74.9 dB SNDR 1 MHz Bandwidth 0.9 mW Delta-Sigma Time-to-Digital Converter Using Charge Pump and SAR ADC

[R. Staszewski, RFIC ‘04] [M. Lee, VLSIC ‘07] Delay line TA Delay line CK1 CK2 Logic Dout Coarse Fine td td Thermal to binary encoder CK1 CK2 Dout td

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ΔΣ TDC Prior Arts

  • Gated Ring Oscillator

 Breaking the technology- limited resolution  Dead-zone issue

  • Switched Ring Oscillator

 No dead-zone issue  Always running VCO → high power

A 74.9 dB SNDR 1 MHz Bandwidth 0.9 mW Delta-Sigma Time-to-Digital Converter Using Charge Pump and SAR ADC

[M.Z. Straayer, JSSC ‘09] [A. Elshazly, JSSC ‘14]

Differentiator Out Clr Tin GRO SRO Differentiator Out Clr VH VL Tin

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Voltage-domain TDC

  • Time-to-voltage followed by analog-to-digital conversion

 More relaxed technology-constrained resolution  High resolution ADC is required

A 74.9 dB SNDR 1 MHz Bandwidth 0.9 mW Delta-Sigma Time-to-Digital Converter Using Charge Pump and SAR ADC

PFD UP DN CK1 CK2 C Dout ADC CLR

  • Typical implementation
  • Charge-pump + SAR ADC

[Z. Xu, CICC ‘13]

  • Charge-pump + ΔΣ ADC

[M.B. Dayanik, ESSCIRC ‘15]

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Mixed-domain ΔΣ TDC

  • Gm-cell as integrator + time-domain feedback

Simplified ADC design Power-starving integrator Only for positive input

A 74.9 dB SNDR 1 MHz Bandwidth 0.9 mW Delta-Sigma Time-to-Digital Converter Using Charge Pump and SAR ADC

[M. Gande, VLSIC ‘12]

Tin Tdtc C

Σ

Gm Dout Counter ADC DTC Фfast Tdtc

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Proposed Mixed-domain ΔΣ TDC

  • Integrator implementation by charge

preservation

Compact design Low power Differential input

A 74.9 dB SNDR 1 MHz Bandwidth 0.9 mW Delta-Sigma Time-to-Digital Converter Using Charge Pump and SAR ADC

PFD UP DN CK1 CK2 C Dout ADC DTC Time sub

Δ TVC and Σ Low- resolution ADC

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Charge-pump as Integrator

  • Bottom-plate sampling

– Reduces charge injection – Prevents charge-pump’s current mismatch

A 74.9 dB SNDR 1 MHz Bandwidth 0.9 mW Delta-Sigma Time-to-Digital Converter Using Charge Pump and SAR ADC

CK1 CK2 UP DN Vo Tin Td ΔVo S1 S2 sampling conversion sampling

𝜠𝑾𝒑 = 𝑱𝐃𝐐 . 𝑼𝐣𝐨 /𝑫𝐣𝐨𝐮

C C U D V Δ D Q R D Q R CK1 CK2 Td UP DN ICP Vo ICP Cint S1 S2 S S

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Charge-sharing Phenomenon

A 74.9 dB SNDR 1 MHz Bandwidth 0.9 mW Delta-Sigma Time-to-Digital Converter Using Charge Pump and SAR ADC

  • Op-amp can

reduce charge- sharing before and after sampling

CK1 CK2 UP DN 2 3

VO

1

Cint

+

  • VO

ICP ICP VM ICP VDD/2 VO Cint Cint

+

  • VO

ICP ICP VM CPN VO Cint Cint

+

  • VO’

ICP ICP VM CPN ICP CPN VO -ΔVO VDD/2 Cint CPN CPP CPP spilled charge spilled charge

  • 1. Before sampling
  • 2. Sampling
  • 3. Sampling finish

equal charge equal charge CPP CPP VDD/2

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Pseudo Diff. Charge-pump

  • Op-amps provide an

isolated CMFB voltage from the actual sampled voltage

A 74.9 dB SNDR 1 MHz Bandwidth 0.9 mW Delta-Sigma Time-to-Digital Converter Using Charge Pump and SAR ADC

nt

VOP Cint VM RM RM CCM1

+

  • VON

Cint

+

  • VMP

VMN UP DN DN UP VBP,CMFB VOP VON VM VCP VCN VBN VBP VCM

+

  • +
  • VMP

VMN DN UP UP DN VCUP VCD

P

VCUN VCD

N

RM RM Ф2 Ф1 CMFB Cint Cint CCM2 CCM1

Ф1 Ф2

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Time-domain Feedback

  • Using delay-line Digital-to-Time Converter (DTC)
  • Input is delayed based on TDC’s output

A 74.9 dB SNDR 1 MHz Bandwidth 0.9 mW Delta-Sigma Time-to-Digital Converter Using Charge Pump and SAR ADC

TIN DIN TOUT …

DTC Time subtraction method

OUT>0 →delay CK1 OUT<0 →delay CK2

CK1 CK2 TIN TIN-TOUT>0 TIN-TOUT<0 Positive input Negative input

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Proposed ΔΣ TDC Architecture

A 74.9 dB SNDR 1 MHz Bandwidth 0.9 mW Delta-Sigma Time-to-Digital Converter Using Charge Pump and SAR ADC

1

Dout > 0 CK1

1

Dout < 0 CK2 UP DN ICP ICP

+ +

Vinp Vdacn

  • Vinn

Vdacp Cint DTC DTC UP DN z-1

SAR Logic

Dout PFD

4-bit SAR ADC Δ TVC and Σ

CDAC CDAC Cint

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TDC Noise Analysis

  • Thermal noise and quantization noise are

the dominant noise sources

A 74.9 dB SNDR 1 MHz Bandwidth 0.9 mW Delta-Sigma Time-to-Digital Converter Using Charge Pump and SAR ADC

65 70 75 80 85 90 2 3 4 5 6 7 SNDR (dB) Quantizer size (bit)

  • 100
  • 95
  • 90
  • 85
  • 80

2 3 4 5 6 7 Noise power (dB) Quantizer size (bit)

Thermal noise dominates Quantization noise dominates Total noise Thermal noise Quantization noise without thermal noise Cint = 2 pF 1 pF 0.5 pF 0.25 pF with thermal noise Cint = 0.5 pF

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SAR ADC Quantizer

  • SAR ADC: low power, low complexity, moderate speed
  • Separated CDAC and charge-pump capacitor

 Reduce disturbance to sampled charge  Smaller CDAC cap for faster conversion

A 74.9 dB SNDR 1 MHz Bandwidth 0.9 mW Delta-Sigma Time-to-Digital Converter Using Charge Pump and SAR ADC

Vrefp Vrefn SAR Logic CDAC Cu Cu 2N-1Cu … Vin

Dout

Vdac +

  • +
  • CK

CK Voutp Voutn CK Vinn Vdacn Vinp Vdacp

[M. Miyahara, A-SSCC ‘08]

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Performance Summary

  • 830 kHz 2.4nspp input at 1 MHz bandwidth, 200 MHz

sampling freq.

A 74.9 dB SNDR 1 MHz Bandwidth 0.9 mW Delta-Sigma Time-to-Digital Converter Using Charge Pump and SAR ADC

  • 100
  • 80
  • 60
  • 40
  • 20

0.1 1 10 100 Normalized PSD (dB) Frequency (MHz) FBW 20 40 60 80

  • 80
  • 60
  • 40
  • 20

SNDR (dB) Input amplitude (dBFS) 20 dB/dec SNDR = 74.9 dB ENOB = 12.1 bit

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Core Layout Implementation

  • Core area:

0.017 mm2

A 74.9 dB SNDR 1 MHz Bandwidth 0.9 mW Delta-Sigma Time-to-Digital Converter Using Charge Pump and SAR ADC

121 μm 142 μm

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Performance Comparison

JSSC ’09 JSSC ‘14 CICC ‘13 ESSCIRC ‘15 VLSIC ‘12 This* ΔΣ TDC Type GRO SRO GSRO CP+ ΔΣ ADC CP+ Gm-C CP+ SAR Filter order 1st 1st 2nd 3rd 3rd 1st CMOS (nm) 130 90 65 65 130 65 Sampling (MHz) 50 500 400 270 90 200 Bandwidth (MHz) 1.0 1.0 4.0 1.0 2.8 1.0 SNDR (dB) 95.0 63.1 80.4 N/A 67.0 74.9

  • Integ. noise (fsrms)

80 315 148 176 866 269 Resolution (ps)** 0.28 1.09 0.51 0.61 3.00 0.63 Power (mW) 21.0 2 6.55 8.4 2.58 0.9 FoM (fJ/conv)*** 227 860 96 N/A 250 99 Area (mm2) 0.04 0.02 0.05 0.055 0.425 0.017

A 74.9 dB SNDR 1 MHz Bandwidth 0.9 mW Delta-Sigma Time-to-Digital Converter Using Charge Pump and SAR ADC

*Transistor-level simulation **Resolution = 12 × integrated noise ***FoM = Power/(2 × bandwidth × 2 (SNDR-1.76)/6.02)

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Conclusion

  • A mixed time and voltage domain TDC is

proposed

  • Charge-pump is used both as VTC and

integrator to achieve low power performance

  • The ΔΣ implementation allows a good TDC

resolution while only using a low bit SAR ADC as quantizer

A 74.9 dB SNDR 1 MHz Bandwidth 0.9 mW Delta-Sigma Time-to-Digital Converter Using Charge Pump and SAR ADC

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Acknowledgement

  • This work was partially supported by MIC,

STARC, HUAWEI, Mentor Graphics for the use of the AFS Platform, and VDEC in collaboration with Cadence Design Systems, Inc.

A 74.9 dB SNDR 1 MHz Bandwidth 0.9 mW Delta-Sigma Time-to-Digital Converter Using Charge Pump and SAR ADC

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A 74.9 dB SNDR 1 MHz Bandwidth 0.9 mW Delta-Sigma Time-to-Digital Converter Using Charge Pump and SAR ADC

Anugerah Firdauzi, Zule Xu, Masaya Miyahara, and Akira Matsuzawa

firdaus@ssc.pe.titech.ac.jp