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A 83-dB SFDR 10-MHz Bandwidth A 83-dB SFDR 10-MHz Bandwidth Continuous-Time Delta-Sigma Modulator Employing a One-Element- M d l t E l i O El t Shifting Dynamic Element Matching Hong Phuc Ninh, Masaya Miyahara, and Akira Matsuzawa

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SLIDE 1

A 83-dB SFDR 10-MHz Bandwidth A 83-dB SFDR 10-MHz Bandwidth Continuous-Time Delta-Sigma M d l t E l i O El t Modulator Employing a One-Element- Shifting Dynamic Element Matching

Hong Phuc Ninh, Masaya Miyahara, and Akira Matsuzawa Akira Matsuzawa Tokyo Institute of Technology, Japan

Matsuzawa & Okada Lab. Matsuzawa & Okada Lab.

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SLIDE 2

1

Outline

  • Background

Background

  • Proposed one-element-shifting

(OES) DEM method (OES) DEM method

  • Implementation and measurement

lt results

  • Conclusion

Matsuzawa & Okada Lab. Matsuzawa & Okada Lab.

2011/11/30 H.P. Ninh, Tokyo Tech.

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SLIDE 3

2

Outline

  • Background

Background

  • Proposed one-element-shifting

(OES) DEM method (OES) DEM method

  • Implementation and measurement

lt results

  • Conclusion

Matsuzawa & Okada Lab. Matsuzawa & Okada Lab.

2011/11/30 H.P. Ninh, Tokyo Tech.

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SLIDE 4

3

Receiver architecture

TV tuner 2G/3G cellular WLAN …

*10 MHz bandwidth (our target design) *High Dynamic Range (DR) *High Spurious-Free Dynamic Range (SFDR)

ΣΔ ADC is a hopeful solution

Matsuzawa & Okada Lab. Matsuzawa & Okada Lab.

2011/11/30 H.P. Ninh, Tokyo Tech.

to achieve high DR & SFDR

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SLIDE 5

4

ΣΔ ADC architecture

N: Quantizer resolution L=4 N: Quantizer resolution OSR: oversampling ratio (=Fs/2/BW) L: filter order L=3 L=4 N=1,2,3,4 150

  • f Fs

Continuous-time ΣΔ ADC with multi-bit quantizer & DAC SNR L=1 L=2 100

DAC linearity i i ation o Our design

S L=1 50

is an issue Low resolution Limita

Matsuzawa & Okada Lab. Matsuzawa & Okada Lab.

2011/11/30 H.P. Ninh, Tokyo Tech.

1 10 100 OSR

L

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SLIDE 6

5

Ci

Linearity issues of feedback DAC

I t t f ΣΔ ADC

Vip Rin Cin Vom V

+ -

N

Input stage of ΣΔ ADC Unity cell

Rin Cin Vop Vim

  • +

P

Static error

in

Static error Mismatch

Inp<0> Inn<0> Inp<1> Inn<1> Inp<7> Inn<7>

1 05 0 98 1 02 Ex: 1.05 0.98 1.02 Ex:

Mismatch deviation Transitor size

Matsuzawa & Okada Lab. Matsuzawa & Okada Lab.

2011/11/30 H.P. Ninh, Tokyo Tech.

For simplicity, a 3bit DAC is considered

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SLIDE 7

6

Linearity issues of feedback DAC

Ci

I t t f ΣΔ ADC

Vip Rin Cin Vom V

+ -

N

Input stage of ΣΔ ADC

Dynamic error

Rin Cin Vop Vim

  • +

P

Dynamic error Glitch

in

Inp<0> Inn<0> Inp<1> Inn<1> Inp<7> Inn<7>

P iti it Normalized glitch energy Parasitic capacitance Non-ideal switching F hi h d ti d i

Matsuzawa & Okada Lab. Matsuzawa & Okada Lab.

2011/11/30 H.P. Ninh, Tokyo Tech.

For high speed operation, dynamic error becomes more critical

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SLIDE 8

7

What is glitch energy?

Switching asymmetry

I (uA) T (ns) Glitch energy (Glitch area)

Matsuzawa & Okada Lab. Matsuzawa & Okada Lab.

2011/11/30 H.P. Ninh, Tokyo Tech.

Glitch energy: average of 8192points

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SLIDE 9

8

Requirements of DAC linearity

Static error Mismatch Dynamic error Glitch

80 90 60 70 40 50 60

0.3% 1.6%

1 2 3 40 4 5

R i t f SNR 70dB

Matsuzawa & Okada Lab. Matsuzawa & Okada Lab.

2011/11/30 H.P. Ninh, Tokyo Tech.

Requirement for SNR>70dB (BW=10MHz, Fs=500MHz)

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9

Outline

  • Motivation

Motivation

  • Proposed one-element-shifting

(OES) DEM method (OES) DEM method

  • Implementation and measurement

lt results

  • Conclusion

Matsuzawa & Okada Lab. Matsuzawa & Okada Lab.

2011/11/30 H.P. Ninh, Tokyo Tech.

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10

DEM topology summary Prop.

OES

DWA-group

(ADWA, Bi-DWA)

TC-group

(RTC, RSTC)

Glitch Good Bad Excellent Mismatch Good Excellent Bad Mismatch Good Excellent Bad

(DEM: to improve DAC linearity)

*Data Weighted Averaging (DWA) [1] *Advanced Random DWA (ADWA) [2] *Bi-directional DWA (Bi-DWA) [3] *Th t C di (TC / DEM) *Thermometer Coding (TC, w/o DEM) *Randomized Thermometer Coding (RTC) [4] *Restricted Swapping Thermometer Coding (RSTC) [5]

[1] R T Baird et al IEEE Trans Circuits Syst II Dec 1995

Matsuzawa & Okada Lab. Matsuzawa & Okada Lab.

2011/11/30 H.P. Ninh, Tokyo Tech. [1] R. T. Baird et al., IEEE Trans. Circuits Syst. II,, Dec. 1995. [2] I. Fujimori et al., IEEE J. Solid-State Circuits, Dec. 2000. [3] D. H. Lee et al., IEEE Trans. Circuits Syst. II, Oct. 2007. [4] D. H. Lee et al., IEEE Trans. Circuits Syst. II, Feb. 2009. [5] M. H. Shen et al., IEEE Trans. Circuits Syst. II, May. 2010.

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OES: Eliminating Effect of Glitch

By reducing the number of switched elements g(n)

(w/ same other glitch conditions)

g(n) Glitch energy

⎩ ⎨ ⎧ > − + − − − ≤ − + − + = N n x n x n x n x N N n x n x n x n x n g ) 1 ( ) ( ), 1 ( ) ( 2 ) 1 ( ) ( ), 1 ( ) ( ) (

⎩ ⎨ ⎧ − < − − − ≥ − − + = ) 1 ( ) ( , ) 1 ( ) ( ) 1 ( ) ( ), 1 ( ) ( 2 ) ( n x n x n x n x n x n x n x n x n g

Matsuzawa & Okada Lab. Matsuzawa & Okada Lab.

2011/11/30 H.P. Ninh, Tokyo Tech.

) 1 ( ) ( ) ( − − = n x n x n g

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Glitch Energy

g(n) Glitch energy

Sim condition *tfb tf trb tr 20ps *tfb-tf=trb-tr=20ps *Cp=10fF *3bit DAC (w/o mismatch) ( )

Matsuzawa & Okada Lab. Matsuzawa & Okada Lab.

2011/11/30 H.P. Ninh, Tokyo Tech.

Requirement for SNR>70dB (BW=10MHz, Fs=500MHz)

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13

OES: Preserve Reduction of Mismatch Effect

By reducing the mismatch error spectrum in the interesting bandwidth

(w/ same mismatch deviation) (w/ same mismatch deviation)

OES (Good) ADWA (Excellent) RSTC (Bad)

pectrum [dB]

  • 40
  • 20

pectrum [dB]

  • 40
  • 20

pectrum [dB]

(Good) (Excellent) (Bad)

AC mismatch sp

120

  • 100
  • 80
  • 60

AC mismatch sp

120

  • 100
  • 80
  • 60

AC mismatch sp DA Frequency [MHz]

50 100 150 200 250

  • 120

DA Frequency [MHz]

50 100 150 200 250

  • 120

DA

(1%mismatch input: 1MHz@ 30dBFS)

Matsuzawa & Okada Lab. Matsuzawa & Okada Lab.

2011/11/30 H.P. Ninh, Tokyo Tech.

(1%mismatch, input: 1MHz@-30dBFS)

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14

Mismatch requirement

Mismatch DAC area

Mismatch

Sim condition *tfb tf trb tr 0ps

Mismatch Relaxation

*tfb-tf=trb-tr=0ps *Cp=10fF *3bit DAC (w/o glitch) ( g )

Matsuzawa & Okada Lab. Matsuzawa & Okada Lab.

2011/11/30 H.P. Ninh, Tokyo Tech.

Requirement for SNR>70dB (BW=10MHz, Fs=500MHz)

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15

With Both of Glitch and Mismatch

90 80 OES w/o DEM

w/glitch w/glitch

70 RTC RSTC 50 60 ADWA Bi-DWA

OES achieves better SNDR & SFDR

50

mismatch

1 2 3

OES achieves better SNDR & SFDR performance over the published DEM methods

Sim condition

Matsuzawa & Okada Lab. Matsuzawa & Okada Lab.

2011/11/30 H.P. Ninh, Tokyo Tech.

Sim condition *tfb-tf=trb-tr=20ps *Cp=10fF *3bit DAC (w/ mismatch)

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16

Outline

  • Background

Background

  • Proposed one-element-shifting

(OES) DEM method (OES) DEM method

  • Implementation and measurement

lt results

  • Conclusion

Matsuzawa & Okada Lab. Matsuzawa & Okada Lab.

2011/11/30 H.P. Ninh, Tokyo Tech.

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17

System architecture

M d l t S Modulator Spec FF+FB, 3rd order 4bit AD/DA BW: 10MHz Fs: 500MHz Fs: 500MHz SNDRreq: 70dB 90nm CMOS process

Matsuzawa & Okada Lab. Matsuzawa & Okada Lab.

2011/11/30 H.P. Ninh, Tokyo Tech.

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18

OES DEM architecture

OES DEM

Example for 4 elements DAC

OES DEM *Simplicity (no extra i t i t ) pointer, no register) *Relax timing requirement f f db k DAC

Matsuzawa & Okada Lab. Matsuzawa & Okada Lab.

2011/11/30 H.P. Ninh, Tokyo Tech.

for feedback DAC

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Modulator layout

OES DEM Core area: 9%

Matsuzawa & Okada Lab. Matsuzawa & Okada Lab.

2011/11/30 H.P. Ninh, Tokyo Tech.

Power consumption: 6%

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20

Measurement Results

w/o DEM OES DEM

Remove by digital filter

OES-DEM

g BW

W/o DEM OES DEM SNDR 62.8 63.3

Matsuzawa & Okada Lab. Matsuzawa & Okada Lab.

2011/11/30 H.P. Ninh, Tokyo Tech.

SFDR 71.8 82.6

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21

Measurement Results

SNDR-w/o DEM SFDR-w/o DEM SNDR-OES DEM SFDR-OES DEM

Average of 10dB SFDR improvement are achieved

Matsuzawa & Okada Lab. Matsuzawa & Okada Lab.

2011/11/30 H.P. Ninh, Tokyo Tech.

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22

Performance Comparison

Unit Unit This work This work [6] [6] [7] 7] [8] [8] Type/ DEM pe/ DEM CT/OES T/OES CT/DW T/DWA DT/DEM T/DEM CT/DW T/DWA B d B d idth MH MH 10 10 20 20 5 10 10 Ban andwidth idth MH MHz 10 10 20 20 5 10 10

  • Samp. freq.
  • Samp. freq.

MHz Hz 500 500 640 640 80 80 300 300 SFDR SFDR dB dB 83 83 77 77* 85 85 64 64* SNDR SNDR dB dB 65 65 63.9 63.9 75.4 75.4 62.5 62.5 DR dB DR dB 66 66 68 68

  • 70.2

70.2 P W 15 15 7 58 58 36 36 5 3 5 31 Power

  • wer

mW 15 15.7 58 58 36 36 5.31 31 CMOS proc. CMOS proc. nm 90 130 130 180 180 110 FoM FoM fJ/conv J/conv 530 530 1130 130 750 750 240 240

*Better SFDR (compared with conv. DEM method) *Less power (w/ same SFDR)

Matsuzawa & Okada Lab. Matsuzawa & Okada Lab.

2011/11/30 H.P. Ninh, Tokyo Tech.

Less power (w/ same SFDR)

[6]J. G. Jo et al., ASSCC Dig. Tech. Papers, Nov. 2010. [7]O. Rajaee et al., IEEE J. Solid-State Circuits, Apr. 2010. [8]K. Matsukawa et al., IEEE Symp. on VLSI Circuits, Jun. 2009.

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23

Outline

  • Background

Background

  • Proposed one-element-shifting

(OES) DEM method (OES) DEM method

  • Implementation and measurement

lt results

  • Conclusion

Matsuzawa & Okada Lab. Matsuzawa & Okada Lab.

2011/11/30 H.P. Ninh, Tokyo Tech.

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24

Conclusion

  • Proposed OES DEM method substantially

suppresses the both effects of mismatch suppresses the both effects of mismatch and glitch.

  • ΣΔ modulator using OES DEM achieves
  • ΣΔ modulator using OES DEM achieves

83dB SFDR and 10dB improvement compared to no DEM compared to no DEM.

  • Simplicity and effectiveness of the OES

technique makes it very attractive and technique makes it very attractive and prefer for cost and power considerations.

Matsuzawa & Okada Lab. Matsuzawa & Okada Lab.

2011/11/30 H.P. Ninh, Tokyo Tech.

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Acknowledgments

This work was supported by CREST, JST, pp y VLSI Design and Education Center (VDEC), the University of Tokyo in collaboration with y y Cadence Design Systems. The authors also acknowledge Berkeley Design Automation for g y g the use of the Analog FastSPICE (AFS) Platform.

Matsuzawa & Okada Lab. Matsuzawa & Okada Lab.

2011/11/30 H.P. Ninh, Tokyo Tech.

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Reference

[1]

  • R. T. Baird and T. S. Fiez, “Linearity enhancement of multibit ∆Σ A/D and D/A converters using

data weighted averaging,” IEEE Trans. Circuits Syst. II, Analog Digit. Signal Process., vol. 42, no. 12, pp. 753–762, Dec. 1995. [2]

  • I. Fujimori, L. Longo, A. Hairapetian, K. Seiyama, S. Kosic, J. Cao, and S. L. Chan, “A 90-dB SNR

2.5-MHz output-rate ADC using cascaded multibit delta-sigma modulation at 8X oversampling ratio,” IEEE J. Solid-State Circuits, vol. 35, no. 12, pp. 1820–1828, Dec. 2000. [3]

  • D. H. Lee, and T. H. Kuo, “Advancing data weighted averaging technique for multi-bit sigma–delta

modulators ,” IEEE Trans. Circuits Syst. II, Exp. Briefs, vol. 54, no. 10, pp. 838–842, Oct. 2007. [4]

  • D. H. Lee, T. H. Kuo, and K. L. Wen, “Low-cost 14-bit current-steering DAC with a randomized

thermometer-coding method,” IEEE Trans. Circuits Syst. II, Exp. Briefs, vol. 56, no. 2, pp. 137– 141 Feb 2009 141, Feb. 2009. [5]

  • M. H. Shen, J. H. Tsai, and P. C. Huang, “Random swapping dynamic element matching

technique for glitch energy minimization in current-steering DAC,” IEEE Trans. Circuits Syst. II,

  • Exp. Briefs, vol. 57, no. 5, pp. 369–373, May. 2010.

[6]

  • J. G. Jo, J. Noh, and C. Yoo, “A 20MHz bandwidth continuous-time Σ∆ modulator with jitter

immunity improved full-clock period SCR (FSCR) DAC and high speed DWA ” ASSCC Dig Tech immunity improved full-clock period SCR (FSCR) DAC and high speed DWA, ASSCC Dig. Tech. Papers, pp. 1-4, Nov. 2010. [7]

  • O. Rajaee, T. Musah, N. Maghari, S. Takeuchi, M. Aniya, K. Hamashita, and U. K. Moon, “Design
  • f a 79 dB 80 MHz 8X-OSR Hybrid Delta-Sigma Pipelined ADC,” IEEE J. Solid-State Circuits, Vol.

45, No. 4, pp. 719-730, Apr. 2010. [8]

  • K. Matsukawa, Y. Mitani, M. Takayama, K. Obata, S. Dosho and A. Matsuzawa, “A 5th-Order

[8]

  • K. Matsukawa, Y. Mitani, M. Takayama, K. Obata, S. Dosho and A. Matsuzawa, A 5th Order

Delta-Sigma Modulator with Single-Opamp Resonator,” IEEE Symp. on VLSI Circuits, pp. 68-69,

  • Jun. 2009.

Matsuzawa & Okada Lab. Matsuzawa & Okada Lab.

2011/11/30 H.P. Ninh, Tokyo Tech.

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Thank you!!!

Matsuzawa & Okada Lab. Matsuzawa & Okada Lab.

2011/11/30 H.P. Ninh, Tokyo Tech.