A 0.5-to-1 V 9-bit 15-to-90 MS/s Digitally Interpolated - PowerPoint PPT Presentation

A 0.5-to-1 V 9-bit 15-to-90 MS/s Digitally Interpolated Pipelined-SAR ADC Using Dynamic Amplifier James Lin, Zule Xu, Masaya Miyahara, and Akira Matsuzawa Tokyo Institute of Technology, Japan b. Matsuzawa & Okada Lab y

Outline • Motivation • Digital Interpolation • Circuit Design • Measurement Results • Conclusion 2

Conventional Pipelined-SAR ADC • Pipelined-SAR ADCs are sensitive to inter-stage gain variation similar to pipelined ADCs Calibration [1]-[3] V in V res D 2 A SAR 1 SAR 2a D 1 n m Digital Error Corr. D out [1] J. Zhong, et al ., A-SSCC 2012 . [2] B. Verbruggen, et al ., VLSI Circuits 2013 . 3 [3] F. van der Goes, et al ., ISSCC 2014.

Analog Interpolation • For pipelined ADCs, interpolation can be used to alleviate absolute gain requirement [4] V ref V refp Any Gain V ia to A 2a A 1a V in Dynamic Amp. V ib V refn to A 2b A 1b 01 11 01 Embedded references [4] J. Lin, et al ., CICC 2013. 4

Outline • Motivation • Digital Interpolation • Circuit Design • Measurement Results • Conclusion 5

Digitally Interpolated Pipelined-SAR • Digital interpolation is proposed for its simplicity and robustness V in V res V a/b A × V a/b t t t t V LSB1 A × V a D 2a SAR 2a V in V res A SAR 1 ± ½LSB D 2b SAR 2b A × V b D 1 V a/b m m n Digital Interpolator D out 6

Insensitive to Inter-Stage Gain • Outputs of the second stage is a fractional representation of the original residue D 2a A × V a SAR 2a V res D 2a = D{ A × ( V res +½ V LSB1 )} A ± ½LSB D 2b D 2b = D{ A × ( V res -½ V LSB1 )} SAR 2b V a or V b A × V b D 2a + D 2b = 2 A × V res A × V a D 2a - D 2b = A × V LSB1 A × V a/b ( D 2a + D 2b )/2 = V res A × V res D 2a - D 2b V LSB1 A × V LSB1 t ( D 2a + D 2b )/2 a D out = ( D 1 + ) × 2 m- A × V b D 2a - D 2b 7

Dynamic Amplifier • High speed at low supply voltage and clock-scalable power consumption [5] Pre-charge Amplification Phase Phase V outn CLK V outp CMD V outp Voltage V oc V out V out V inp V inn V outn CLK CLK Time 2 CMD: Common-mode voltage detector P d = fCV DD [5] J. Lin, et al., ISCAS 2011. 8

Inter-Stage Gain Variation • Dynamic amplifier’s gain varies with supply voltage  digital interpolation suppresses the ENOB degradation G amp = a ( V DD - V oc )/ V eff , 1< a <2 D G/G vs. Supply ENOB vs. D G/G 50 9.0 40 ENOB (bit) 8.5 D G/G (%) 30 ENOB (bit) dG/G (%) 8.0 20 7.5 10 Conventional Proposed 7.0 0 0.5 0.6 0.7 0.8 0.9 1.0 0 5 10 15 20 25 30 D G/G (%) Supply voltage (V) Supply voltage (V) dG/G (%) 9

Up/Down Shift Error • Interpolation requires an accurate shift instead of the conventional accurate gain D C / C ≈ 0.45%(3 s ) 9.0 ENOB (bit) 8.5 ENOB (bit) 8.0 7.5 Calculated Simulated 7.0 0 5 10 15 20 25 30 D V LSB1 /V LSB1 (%) dVs/Vs (%) 10

Outline • Motivation • Digital Interpolation • Circuit Design • Measurement Results • Conclusion 11

Circuit Design Overview • ADC architecture • Self-clocking scheme • Shared dynamic amplifier • Ultra-low-voltage SAR ADCs 12

ADC Architecture • Proposed ADC consists of two stages  6b SAR ADC, 2×sampling CDACs, logic  Dynamic amplifier, 2×6b SAR ADCs, logic On-Chip SW h <0> SW s <0> V a/b Sampling CDAC 1 Amp Logic CLK sar<1:0> CLK amp A × V a SAR 2a (6b) V in Timing SAR 1 D. Amp SW s <1:0> Logic (6b) (A) SAR 2b CLK SW h <1:0> A × V b (6b) Sampling CDAC 2 Digital SW h <1> SW s <1> D out Interpolator 13

Self-Clocking • Simulated timing diagram to show the key steps Start SAR 1 Reset 7 1 Sample SAR 1 (SAR 1 ) 2 4 5 Code transfer and upshift Sample CDAC 1 +½ LSB -½ LSB (CDAC 1 ) Downshift CDAC 2 +½ LSB -½ LSB Amplify upshifted AMP SAR2a V res,CDAC2 for SAR 2a Start SAR 2a 3 Sample SAR 2a Conv. (SAR 2a ) Amplify downshifted AMP SAR2b V res,CDAC2 for SAR 2b Start SAR 2b 6 Sample SAR 2b Conv. (SAR 2b ) 14 Time

Shared Dynamic Amplifier • Same pair of amplifying transistors are shared between the two second-stage SAR ADCs SAR 2a SAR 2b V ap V an V bp V bn CMD CMD V inp V inn CMD 15

Ultra-Low-Voltage SAR ADCs • Virtual V cm realized using capacitive interpolation achieves high speed V ap V an C u /2 C u /2 C u /2 C u /2 2 × C u /2 2 × C u /2 16 × C u /2 16 × C u /2 V refp V refn 16

Outline • Motivation • Digital Interpolation • Circuit Design • Measurement Results • Conclusion 17

Measured DNL and INL (0.6 V) • DNL: +0.81/-0.40 LSB • INL: +0.69/-0.85 LSB 1.5 1.5 1.0 1.0 DNL (LSB) INL (LSB) 0.5 0.5 DNL (LSB) INL (LSB) 0.0 0.0 -0.5 -0.5 -1.0 -1.0 -1.5 -1.5 0 128 256 384 512 0 128 256 384 512 Digital code Digital code Digital code Digital code 18

Measured SNDR and SFDR (0.6 V) • >49 dB of SNDR is measured up to 30 MS/s with an ERBW >15 MHz • Consumes 481.6 m W (23% analog, 65% digital, 12% reference) at 30 MS/s  FoM=68 fJ/conversion-step SNDR & SFDR vs. f s SNDR & SFDR vs. f in SNDR and SFDR (dB) SNDR and SFDR (dB) 70 70 65 65 SFDR and SNDR (dB) SFDR and SNDR (dB) 60 60 55 55 50 50 45 45 f in = 1 MHz 40 40 f s = 30 MS/s SFDR SFDR 35 35 SNDR SNDR 30 30 5 10 15 20 25 30 35 0.0 2.5 5.0 7.5 10.0 12.5 15.0 Conversion rate (MS/s) Input frequency (MHz) Conversion rate (MS/s) Input frequency (MHz) 19

Measured SNDR and SFDR ( 0.6-1.0 V) • 0.6 V  30 MS/s, 68 fJ/conversion-step • 0.8 V  70 MS/s, 148 fJ/conversion-step • 1.0 V  90 MS/s, 247 fJ/conversion-step SNDR & SFDR vs. f s SNDR & SFDR vs. f in SNDR and SFDR (dB) SNDR and SFDR (dB) 70 70 V DD = 0.6 V V DD = 0.6 V f s = 30 MS/s V DD = 1.0 V 60 60 f s = 90 MS/s V DD = 0.8 V V DD = 0.8 V V DD = 1.0 V f s = 70 MS/s SFDR (dB) SFDR (dB) 50 50 f in = 1 MHz 40 40 SFDR @ 0.6 V SNDR @ 0.6 V SFDR @ 0.6 V SNDR @ 0.6 V SFDR @ 0.8 V SNDR @ 0.8 V SFDR @ 0.8 V SNDR @ 0.8 V SFDR @ 1.0 V SNDR @ 1.0 V SFDR @ 1.0 V SNDR @ 1.0 V 30 30 0 20 40 60 80 100 120 140 0 10 20 30 40 50 Conversion rate (MS/s) Input frequency (MHz) Conversion rate (MS/s) Input frequency (MHz) 20

Voltage-Scalable Conversion Rate • Conversion rate scales with the supply voltage Conversion rate (MS/s) 100 80 Max. rate (MS/s) 60 40 20 0 0.5 0.6 0.7 0.8 0.9 1.0 Supply voltage (V) Supply voltage (V) 21

Third-Order Harmonic Distortion • ENOB degradation of the prototype ADC is due to noise and a spur caused by interleaved CDACs • 3 rd -order harmonic spur is <-65 dB 0 0 -20 - 2 0 Normalized power (dB) 69.12 dB -40 - 4 0 -60 2 3 - 6 0 -80 - 8 0 -100 - 1 0 0 -120 - 1 2 0 0 0 2 4 5 6 8 1 0 10 1 2 1 4 15 MHz 1 6 0 0 -20 - 2 0 65.97 dB -40 - 4 0 2 3 -60 - 6 0 -80 - 8 0 -100 - 1 0 0 -120 - 1 2 0 0 2 4 6 8 1 0 1 2 1 4 1 6 0 5 10 15 MHz 22

Inter-Stage Gain Variation • Prototype ADC can operation in two modes:  Digital interpolation (proposed)  External gain adjustment (conventional) 56 54 SNR (dB) 52 SNR (dB) >4 dB 50 f s = 30 MS/s, f in = 1 MHz 48 Proposed Conventional 46 0.6 0.7 0.8 0.9 1.0 Supply voltage (V) Supply voltage (V) 23

Clock-Scalable Power Consumption • Dynamic nature of the entire ADC  Power scales with the clock 5.0 Power consumption (mW) Power (mW) 4.0 3.0 2.0 V DD =0.6 V 1.0 V DD =0.8 V 0.0 V DD =1.0 V 0 20 40 60 80 100 120 140 Conversion rate (MS/s) Sampling frequency (MS/s) 24

Chip Photo • Prototype ADC is fabricated in 65 nm CMOS with the low threshold and deep N-well options • The occupied area is <0.11 mm 2 350 m m Sampling SAR 2a CDAC 1 300 m m Amp SAR 1 Sampling SAR 2b CDAC 2 25

Performance Comparison • Digital interpolation and dynamic amplifier realize a flexible ADC [6] [7] [8] This work Architecture Pipe Pipe Pipe Pipelined-SAR Resolution (bit) 8 10 12 9 Supply voltage (V) 0.5 0.5 0.8 0.5 0.6 0.8 1.0 0.5 0.6 0.8 1.0 Conv. rate (MS/s) 10 10 60 5 10 30 50 15 30 70 90 Power (mW) 2.4 3.0 19.2 0.24 0.56 1.61 4.07 0.20 0.48 1.92 3.14 ENOB (bit) 7.7 8.5 8.2 10.7 10.8 10.8 11.0 7.63 7.88 7.54 7.14 FoM (fJ/c.-s.) 1150 825 1118 28.0 30.9 31.1 41 67 68 148 247 Technology (nm) 90 130 65 65 Active area (mm 2 ) 1.44 0.98 0.36 0.11 [6] J. Shen, et al ., JSSC 2008 . [8] S. Lee, et al ., JSSC 2012 . 26 [7] Y. J. Kim, et al ., CICC 2007 .

Outline • Motivation • Digital Interpolation • Circuit Design • Measurement Results • Conclusion 27

Conclusion • Digital interpolation is validated through a 0.5-to-1 V, 9b, 15-to-90 MS/s pipelined-SAR ADC • Proposed digitally interpolated pipelined- SAR ADC achieves  Robustness to gain variation  Voltage-scalable  Clock-scalable 28

Acknowledgement This work was partially supported by NEDO, Huawei, Berkeley Design Automation for the use of the Analog FastSPICE (AFS) Platform, and VDEC in collaboration with Cadence Design Systems, Inc. 29

Thank you for your interest! James Lin, james@ssc.pe.titech.ac.jp 30