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A 1MS/s to 1GS/s Ringamp-Based Pipelined ADC with Fully Dynamic Reference Regulation and Stochastic Scope-on-Chip Background Monitoring in 16nm Benjamin Hershberg, Nereo Markulic, Jorge Lagos, Ewout Martens, Davide Dermit, Jan Craninckx imec,

slide-1
SLIDE 1

2020 Symposia on VLSI Technology and Circuits CD1.1

A 1MS/s to 1GS/s Ringamp-Based Pipelined ADC with Fully Dynamic Reference Regulation and Stochastic Scope-on-Chip Background Monitoring in 16nm

Benjamin Hershberg, Nereo Markulic, Jorge Lagos, Ewout Martens, Davide Dermit, Jan Craninckx imec, Leuven, Belgium

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SLIDE 2

2020 Symposia on VLSI Technology and Circuits CD1.1

Architecture Overview

  • Ringamp “deep” pipeline based on:

[Hershberg, ISSCC 2019, Paper 3.6] [Hershberg, ISSCC 2019, Paper 3.1] – Fully Dynamic Power Consumption – Asynchronous event-driven timing control – MDAC with passive-hold mode in STG1 – Early quantization in STG2-9

Slide 1

c c

master clock INm

c

INp

c

VREFP ext.

c

VCM ext.

c

VREFM ext.

VREFP dirty VREFP clean VCM VREFM dirty VREFM clean

reference regulator BACKEND 1.5b + 3b CTOT= 256fF STG1 1.5b CTOT= 256fF STG2 1.5b CTOT= 128fF STG3 1.5b CTOT= 128fF STG4 1.5b CTOT= 128fF STG5 1.5b CTOT= 128fF STG6 1.5b CTOT= 128fF STG7 1.5b CTOT= 128fF

  • New in this work:

– Reference Regulation – Stochastic Scope-on-Chip – Ringamp Topology

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SLIDE 3

2020 Symposia on VLSI Technology and Circuits CD1.1

Outline

  • Ringamp Topology
  • Fully Dynamic Reference Regulation
  • Scope-on-Chip Amplifier Settling Monitor
  • Performance Summary & Conclusion

Slide 2

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SLIDE 4

2020 Symposia on VLSI Technology and Circuits CD1.1

Ringamp Topology

Slide 3

  • What is a ringamp?

– Multi-stage amplifier – Dominant output pole – Dynamic stabilization ☺ High efficiency ☺ High linearity ☺ High speed ☺ Wide output swing ☺ Fully dynamic (switchable) ☺ Scales with Digital [Hershberg, JSSC 2012]

OUTm INp

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SLIDE 5

2020 Symposia on VLSI Technology and Circuits CD1.1

VDD DZP EN DZN VSS OUTm VDD VSS EN INp VDD DZP EN DZN VSS OUTp INm EN OUTp

B1

CFB CSMALL CBIG

EN

CSENSE

Trapped Charge CMFB

Dz_nmos[7:0] 7 VDD DZN EN Dz_pmos[7:0] 7 VSS DZP EN

Trapped-Charge Bias Control

CFB OUTm CSENSE

EN EN EN

EN EN EN

Ringamp Topology

Slide 4

  • Fully-Differential
  • Multi-Path CMFB
  • Trapped-Charge

Biasing

  • CMOS-Resistor
  • Bias-Enhanced
  • Self-Resetting
  • Slew-Done Detector
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SLIDE 6

2020 Symposia on VLSI Technology and Circuits CD1.1

VDD DZP EN DZN VSS OUTm VDD VSS EN INp VDD DZP EN DZN VSS OUTp INm EN OUTp

B1

CFB CSMALL CBIG

EN

CSENSE

Trapped Charge CMFB

Dz_nmos[7:0] 7 VDD DZN EN Dz_pmos[7:0] 7 VSS DZP EN

Trapped-Charge Bias Control

CFB OUTm CSENSE

EN EN EN

EN EN EN

Ringamp Topology

Slide 5

  • Fully-Differential
  • Multi-Path CMFB
  • Trapped-Charge

Biasing

  • CMOS-Resistor
  • Bias-Enhanced
  • Self-Resetting
  • Slew-Done Detector

[Lim, JSSC Dec. 2015]

slide-7
SLIDE 7

2020 Symposia on VLSI Technology and Circuits CD1.1

VDD DZP EN DZN VSS OUTm VDD VSS EN INp VDD DZP EN DZN VSS OUTp INm EN OUTp

B1

CFB CSMALL CBIG

EN

CSENSE

Trapped Charge CMFB

Dz_nmos[7:0] 7 VDD DZN EN Dz_pmos[7:0] 7 VSS DZP EN

Trapped-Charge Bias Control

CFB OUTm CSENSE

EN EN EN

EN EN EN

Ringamp Topology

Slide 6

  • Fully-Differential
  • Multi-Path CMFB
  • Trapped-Charge

Biasing

  • CMOS-Resistor
  • Bias-Enhanced
  • Self-Resetting
  • Slew-Done Detector

[Lim, JSSC Dec. 2015] [Hershberg, ISSCC 2019] (Paper 3.1)

slide-8
SLIDE 8

2020 Symposia on VLSI Technology and Circuits CD1.1

VDD DZP EN DZN VSS OUTm VDD VSS EN INp VDD DZP EN DZN VSS OUTp INm EN OUTp

B1

CFB CSMALL CBIG

EN

CSENSE

Trapped Charge CMFB

Dz_nmos[7:0] 7 VDD DZN EN Dz_pmos[7:0] 7 VSS DZP EN

Trapped-Charge Bias Control

CFB OUTm CSENSE

EN EN EN

EN EN EN

Ringamp Topology

Slide 7

  • Fully-Differential
  • Multi-Path CMFB
  • Trapped-Charge

Biasing

  • CMOS-Resistor
  • Bias-Enhanced
  • Self-Resetting
  • Slew-Done Detector

[Hershberg, ISSCC 2019] (Paper 3.1)

slide-9
SLIDE 9

2020 Symposia on VLSI Technology and Circuits CD1.1

VDD DZP EN DZN VSS OUTm VDD VSS EN INp VDD DZP EN DZN VSS OUTp INm EN OUTp

B1

CFB CSMALL CBIG

EN

CSENSE

Trapped Charge CMFB

Dz_nmos[7:0] 7 VDD DZN EN Dz_pmos[7:0] 7 VSS DZP EN

Trapped-Charge Bias Control

CFB OUTm CSENSE

EN EN EN

EN EN EN

Ringamp Topology

Slide 8

  • Fully-Differential
  • Multi-Path CMFB
  • Trapped-Charge

Biasing

  • CMOS-Resistor
  • Bias-Enhanced
  • Self-Resetting
  • Slew-Done Detector

[Lagos, JSSC Feb. 2019]

slide-10
SLIDE 10

2020 Symposia on VLSI Technology and Circuits CD1.1

VDD DZP EN DZN VSS OUTm VDD VSS EN INp VDD DZP EN DZN VSS OUTp INm EN OUTp

B1

CFB CSMALL CBIG

EN

CSENSE

Trapped Charge CMFB

Dz_nmos[7:0] 7 VDD DZN EN Dz_pmos[7:0] 7 VSS DZP EN

Trapped-Charge Bias Control

CFB OUTm CSENSE

EN EN EN

EN EN EN

Ringamp Topology

Slide 9

  • Fully-Differential
  • Multi-Path CMFB
  • Trapped-Charge

Biasing

  • CMOS-Resistor
  • Bias-Enhanced
  • Self-Resetting
  • Slew-Done Detector

[Chen, TCASII 2018] [Lagos, JSSC Mar. 2019]

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SLIDE 11

2020 Symposia on VLSI Technology and Circuits CD1.1

VDD DZP EN DZN VSS OUTm VDD VSS EN INp VDD DZP EN DZN VSS OUTp INm EN OUTp

B1

CFB CSMALL CBIG

EN

CSENSE

Trapped Charge CMFB

Dz_nmos[7:0] 7 VDD DZN EN Dz_pmos[7:0] 7 VSS DZP EN

Trapped-Charge Bias Control

CFB OUTm CSENSE

EN EN EN

EN EN EN

Ringamp Topology

Slide 10

  • Fully-Differential
  • Multi-Path CMFB
  • Trapped-Charge

Biasing

  • CMOS-Resistor
  • Bias-Enhanced
  • Self-Resetting
  • Slew-Done Detector

[Lagos, JSSC Mar. 2019]

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SLIDE 12

2020 Symposia on VLSI Technology and Circuits CD1.1

OUTm VDD VSS INp OUTp INm

B1

OUTp CFB CSMALL CBIG

EN

CSENSE

Trapped Charge CMFB

Dz_nmos[7:0] 7 VDD DZN EN Dz_pmos[7:0] 7 VSS DZP EN

Trapped-Charge Bias Control

CFB OUTm CSENSE

EN EN EN

Ringamp Topology

Slide 11

  • Fully-Differential
  • Multi-Path CMFB
  • Trapped-Charge

Biasing

  • CMOS-Resistor
  • Bias-Enhanced
  • Self-Resetting
  • Slew-Done Detector

[Lagos, JSSC Mar. 2019]

slide-13
SLIDE 13

2020 Symposia on VLSI Technology and Circuits CD1.1

Ringamp Topology

Slide 12

  • Fully-Differential
  • Multi-Path CMFB
  • Trapped-Charge

Biasing

  • CMOS-Resistor
  • Bias-Enhanced
  • Self-Resetting
  • Slew-Done Detector

[Hershberg, ISSCC 2019] (Paper 3.6)

slew done detected slew done detected

INm + INp

B A

OUTp

D C

OUTm

EN EN EN EN

BN BP BP BN

slew done

EN

slew done detector td

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SLIDE 14

2020 Symposia on VLSI Technology and Circuits CD1.1

Ringamp Topology

Slide 13

  • Fully-Differential
  • Multi-Path CMFB
  • Trapped-Charge

Biasing

  • CMOS-Resistor
  • Bias-Enhanced
  • Self-Resetting
  • Slew-Done Detector

[Hershberg, ISSCC 2019] (Paper 3.6)

slew done detected slew done detected

INm + INp

B A

OUTp

D C

OUTm

EN EN EN EN

BN BP BP BN

slew done

EN

slew done detector td

Not Mandatory Using a fixed time- delay to generate slew done also ok.

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SLIDE 15

2020 Symposia on VLSI Technology and Circuits CD1.1

Outline

  • Ringamp Topology
  • Fully Dynamic Reference Regulation
  • Scope-on-Chip Amplifier Settling Monitor
  • Performance Summary & Conclusion

Slide 14

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2020 Symposia on VLSI Technology and Circuits CD1.1

Fully Dynamic Reference Regulation

  • Goal: fully dynamic power for complete system (core + reference)

– Constant FoM for any clock rate – Enables reconfigurable, multi-standard ADCs

  • ADC core fully dynamic by design ✓

– Enabler: Asynchronous timing control – Enabler: Ring amplifier with fast on/off switching

  • Reference Regulation

– How can we make this fully dynamic too?

Slide 15

[Hershberg, ISSCC 2019, Paper 3.6]

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SLIDE 17

2020 Symposia on VLSI Technology and Circuits CD1.1

Fully Dynamic Reference Regulation

  • Discrete Time Regulator Loop

– Comparator monitors replica level – Feeds back “charge packet” (CP) update into charge reservoir (CR)

Slide 16

prepare connect

[Kull, JSSC 2013]

Charge source

VREF ext.

prepare

CR

VDD prepare

CP replica out

connect +

Rload

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2020 Symposia on VLSI Technology and Circuits CD1.1

Fully Dynamic Reference Regulation

  • Discrete Time Regulator Loop

– Comparator monitors replica level – Feeds back “charge packet” (CP) update into charge reservoir (CR)

  • Limitations

– Must source all charge for an ADC conversion in a single charge packet – Reference ripple error a problem – Acceptable for ADCs < 8 bit – CR too large for ADCs > 8 bit (> 1nF)

Slide 17

prepare connect

[Kull, JSSC 2013]

Charge source

VREF ext.

prepare

CR

VDD prepare

CP replica out

connect +

Rload

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SLIDE 19

2020 Symposia on VLSI Technology and Circuits CD1.1

Proposed: Split-Reference Regulation

  • Key observation: VREF accuracy &

current requirements are decoupled w.r.t. time

– Initial: large current, low accuracy – Final: small current, high accuracy

Slide 18

Example Settling Waveform

VREF

OUT

sub-DAC

IN

Ringamp

amplify track early amplify track track

X

Example 1.5b flip-around MDAC

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SLIDE 20

2020 Symposia on VLSI Technology and Circuits CD1.1

Proposed: Split-Reference Regulation

  • Key observation: VREF accuracy &

current requirements are decoupled w.r.t. time

– Initial: large current (98%), low accuracy – Final: small current (2%), high accuracy

Slide 19

Example Settling Waveform

VREF

OUT

sub-DAC

IN

Ringamp

amplify track early amplify track track

X

Example 1.5b flip-around MDAC

slide-21
SLIDE 21

2020 Symposia on VLSI Technology and Circuits CD1.1

Proposed: Split-Reference Regulation

  • Key observation: VREF accuracy &

current requirements are decoupled w.r.t. time

– Initial: large current (98%), low accuracy – Final: small current (2%), high accuracy

Slide 20

Example Settling Waveform

VREF

OUT

sub-DAC

IN

Ringamp

amplify track early amplify track track

X

Example 1.5b flip-around MDAC

slide-22
SLIDE 22

2020 Symposia on VLSI Technology and Circuits CD1.1

Proposed: Split-Reference Regulation

  • Key observation: VREF accuracy &

current requirements are decoupled w.r.t. time

– Initial: large current (98%), low accuracy – Final: small current (2%), high accuracy

Slide 21

Example Settling Waveform

VREF

OUT

sub-DAC

IN

Ringamp

amplify track early amplify track track

X

Example 1.5b flip-around MDAC True for many applications

  • Residue Amplifiers

(Slew->Settle)

  • SAR DACs

(MSB->LSB)

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SLIDE 23

2020 Symposia on VLSI Technology and Circuits CD1.1

Proposed: Split-Reference Regulation

  • Solution: Use 2 copies of VREF

– VREF dirty: low-impedance, low-accuracy – VREF clean: high-impedance, high-accuracy

  • Relaxes requirements of both copies

Slide 22

Example Settling Waveform Example 1.5b flip-around MDAC

REF dirty REF clean

OUT

sub-DAC

IN

slew done Ringamp

amplify track early amplify track track

X

slide-24
SLIDE 24

2020 Symposia on VLSI Technology and Circuits CD1.1

Switching from Dirty to Clean Reference

  • Need break-before-make

– Must isolate clean from dirty

Slide 23

Example Settling Waveform Example 1.5b flip-around MDAC

REF dirty REF clean

OUT

sub-DAC

IN

slew done Ringamp

amplify track early amplify track track

X

crossover glitch

slide-25
SLIDE 25

2020 Symposia on VLSI Technology and Circuits CD1.1

Switching from Dirty to Clean Reference

  • Need break-before-make

– Must isolate clean from dirty

  • Want fast & clean crossover

– Amplifier feedback is “paused”, time lost – Any injected errors must be re-settled

Slide 24

Example Settling Waveform Example 1.5b flip-around MDAC

REF dirty REF clean

OUT

sub-DAC

IN

slew done Ringamp

amplify track early amplify track track

X

crossover glitch

slide-26
SLIDE 26

2020 Symposia on VLSI Technology and Circuits CD1.1

Sub-DAC Design Details

  • Optimized control logic

– Non-overlap – Fast crossover (< 30ps) – No corruption of REF_clean

  • Dummy switches to cancel

clock feedthrough & charge injection

  • Minimal impact on

settling performance ✓

Slide 25

Simplified MDAC INp

VCM 1.5b sub-ADC DOUT[1:0] Ringamp +

  • 1.5b

sub-DAC

slew-done

c c c c

INm OUTp OUTm Split-reference sub-DAC

DOUT[1] DOUT[0] amplify slew-done sample early (of next stage) VREFP_clean VREFP_dirty VREFM_dirty VREFP_clean VCM DACp DACm

slide-27
SLIDE 27

2020 Symposia on VLSI Technology and Circuits CD1.1

Sub-DAC Design Details

  • Optimized control logic

– Non-overlap – Fast crossover (< 30ps) – No corruption of REF_clean

  • Dummy switches to cancel

clock feedthrough & charge injection

  • Minimal impact on

settling performance ✓

Slide 26

Simplified MDAC INp

VCM 1.5b sub-ADC DOUT[1:0] Ringamp +

  • 1.5b

sub-DAC

slew-done

c c c c

INm OUTp OUTm Split-reference sub-DAC

DOUT[1] DOUT[0] amplify slew-done sample early (of next stage) VREFP_clean VREFP_dirty VREFM_dirty VREFP_clean VCM DACp DACm

slide-28
SLIDE 28

2020 Symposia on VLSI Technology and Circuits CD1.1

Sub-DAC Design Details

  • Optimized control logic

– Non-overlap – Fast crossover (< 30ps) – No corruption of REF_clean

  • Dummy switches to cancel

clock feedthrough & charge injection

  • Minimal impact on

settling performance ✓

Slide 27

Simplified MDAC INp

VCM 1.5b sub-ADC DOUT[1:0] Ringamp +

  • 1.5b

sub-DAC

slew-done

c c c c

INm OUTp OUTm Split-reference sub-DAC

DOUT[1] DOUT[0] amplify slew-done sample early (of next stage) VREFP_clean VREFP_dirty VREFM_dirty VREFP_clean VCM DACp DACm

slide-29
SLIDE 29

2020 Symposia on VLSI Technology and Circuits CD1.1

Reference Generation

  • Single set of regulated references shared by all stages

– Regulators only update once per cycle

Slide 28

c c

master clock INm

c

INp

c

VREFP ext.

c

VCM ext.

c

VREFM ext.

VREFP dirty VREFP clean VCM VREFM dirty VREFM clean

reference regulator BACKEND 1.5b + 3b CTOT= 256fF STG1 1.5b CTOT= 256fF STG2 1.5b CTOT= 128fF STG3 1.5b CTOT= 128fF STG4 1.5b CTOT= 128fF STG5 1.5b CTOT= 128fF STG6 1.5b CTOT= 128fF STG7 1.5b CTOT= 128fF

slide-30
SLIDE 30

2020 Symposia on VLSI Technology and Circuits CD1.1

Global Reference Generation

Slide 29

  • Standard Pipeline

– VREFP – VCM – VREFM

  • Here: 5 discrete-time loops

– VREFP dirty – VREFP clean – VCM – VREFM dirty – VREFM clean

Pull-up (block 1) Bi-directional (block 3) Bi-directional (block 3) VREFP ext. VREFP_dirty VREFP_clean VCM ext. VCM Pull-down (block 2) Bi-directional (block 3) VREFM ext. VREFM_dirty VREFM_clean

c c

master clock INm

c

INp

c

VREFP ext.

c

VCM ext.

c

VREFM ext.

VREFP dirty VREFP clean VCM VREFM dirty VREFM clean

reference regulator BACKEND 1.5b + 3b CTOT= 256fF STG1 1.5b CTOT= 256fF STG2 1.5b CTOT= 128fF STG3 1.5b CTOT= 128fF STG4 1.5b CTOT= 128fF STG5 1.5b CTOT= 128fF STG6 1.5b CTOT= 128fF STG7 1.5b CTOT= 128fF

slide-31
SLIDE 31

2020 Symposia on VLSI Technology and Circuits CD1.1

Global Reference Generation

Slide 30

  • Standard Pipeline

– VREFP – VCM – VREFM

  • Here: 5 discrete-time loops

– VREFP dirty – VREFP clean – VCM – VREFM dirty – VREFM clean

Pull-up (block 1) Bi-directional (block 3) Bi-directional (block 3) VREFP ext. VREFP_dirty VREFP_clean VCM ext. VCM Pull-down (block 2) Bi-directional (block 3) VREFM ext. VREFM_dirty VREFM_clean

c c

master clock INm

c

INp

c

VREFP ext.

c

VCM ext.

c

VREFM ext.

VREFP dirty VREFP clean VCM VREFM dirty VREFM clean

reference regulator BACKEND 1.5b + 3b CTOT= 256fF STG1 1.5b CTOT= 256fF STG2 1.5b CTOT= 128fF STG3 1.5b CTOT= 128fF STG4 1.5b CTOT= 128fF STG5 1.5b CTOT= 128fF STG6 1.5b CTOT= 128fF STG7 1.5b CTOT= 128fF

1 “Dirty” VCM is enough Common-mode ripple is inherently rejected in differential structure

slide-32
SLIDE 32

2020 Symposia on VLSI Technology and Circuits CD1.1

Global Reference Generation

Slide 31

  • Uni-directional feedback for

dirty references

– MDAC always sinks charge from VREFP dirty – MDAC always sources charge to VREFM dirty

Pull-up (block 1) Bi-directional (block 3) Bi-directional (block 3) VREFP ext. VREFP_dirty VREFP_clean VCM ext. VCM Pull-down (block 2) Bi-directional (block 3) VREFM ext. VREFM_dirty VREFM_clean

c c

master clock INm

c

INp

c

VREFP ext.

c

VCM ext.

c

VREFM ext.

VREFP dirty VREFP clean VCM VREFM dirty VREFM clean

reference regulator BACKEND 1.5b + 3b CTOT= 256fF STG1 1.5b CTOT= 256fF STG2 1.5b CTOT= 128fF STG3 1.5b CTOT= 128fF STG4 1.5b CTOT= 128fF STG5 1.5b CTOT= 128fF STG6 1.5b CTOT= 128fF STG7 1.5b CTOT= 128fF

VDD prepare connect

CP

Charge source

VREFP_ext

prepare

CR

+

slide-33
SLIDE 33

2020 Symposia on VLSI Technology and Circuits CD1.1

Global Reference Generation

Slide 32

  • Uni-directional feedback for

dirty references

– MDAC always sinks charge from VREFP dirty – MDAC always sources charge to VREFM dirty

Pull-up (block 1) Bi-directional (block 3) Bi-directional (block 3) VREFP ext. VREFP_dirty VREFP_clean VCM ext. VCM Pull-down (block 2) Bi-directional (block 3) VREFM ext. VREFM_dirty VREFM_clean

c c

master clock INm

c

INp

c

VREFP ext.

c

VCM ext.

c

VREFM ext.

VREFP dirty VREFP clean VCM VREFM dirty VREFM clean

reference regulator BACKEND 1.5b + 3b CTOT= 256fF STG1 1.5b CTOT= 256fF STG2 1.5b CTOT= 128fF STG3 1.5b CTOT= 128fF STG4 1.5b CTOT= 128fF STG5 1.5b CTOT= 128fF STG6 1.5b CTOT= 128fF STG7 1.5b CTOT= 128fF

Charge sink

VREFM_ext

prepare

CR

VSS prepare

CM

connect +

slide-34
SLIDE 34

2020 Symposia on VLSI Technology and Circuits CD1.1

Global Reference Generation

Slide 33

  • Bi-directional feedback for

clean references and VCM

– Must be able to sink or source

Pull-up (block 1) Bi-directional (block 3) Bi-directional (block 3) VREFP ext. VREFP_dirty VREFP_clean VCM ext. VCM Pull-down (block 2) Bi-directional (block 3) VREFM ext. VREFM_dirty VREFM_clean

c c

master clock INm

c

INp

c

VREFP ext.

c

VCM ext.

c

VREFM ext.

VREFP dirty VREFP clean VCM VREFM dirty VREFM clean

reference regulator BACKEND 1.5b + 3b CTOT= 256fF STG1 1.5b CTOT= 256fF STG2 1.5b CTOT= 128fF STG3 1.5b CTOT= 128fF STG4 1.5b CTOT= 128fF STG5 1.5b CTOT= 128fF STG6 1.5b CTOT= 128fF STG7 1.5b CTOT= 128fF

VDD prepare

CP

VSS prepare

CM

Charge source / sink

CR

VREF_ext

prepare + connect connect

slide-35
SLIDE 35

2020 Symposia on VLSI Technology and Circuits CD1.1

VDD prepare

CP

VSS prepare

CM

Charge source / sink

CR

VREF_ext

prepare +

replica out

connect connect

Regulator Design Considerations

Slide 34

  • CP / CM sizing

– Determined by max current pulled by load

  • CR sizing

– Determined by reference ripple amplitude requirements (accuracy / noise)

slide-36
SLIDE 36

2020 Symposia on VLSI Technology and Circuits CD1.1

VDD prepare

CP

VSS prepare

CM

Charge source / sink

CR

VREF_ext

prepare +

replica out

connect connect

Regulator Design Considerations

  • CP / CM sizing

– Determined by max current pulled by load

  • CR sizing

– Determined by reference ripple amplitude requirements (accuracy / noise)

Slide 35

slide-37
SLIDE 37

2020 Symposia on VLSI Technology and Circuits CD1.1

Regulator Design Considerations

  • Dirty REF accuracy limited by

reference ripple

– Function of CP/CM vs. CR

  • Clean REF accuracy limited by

comparator noise

– Over-designed for low-noise – Can decimate to save power (only operate once every N cycles)

Slide 36

VDD prepare

CP

VSS prepare

CM

Charge source / sink

CR

VREF_ext

prepare +

replica out

connect connect

slide-38
SLIDE 38

2020 Symposia on VLSI Technology and Circuits CD1.1

Regulator Design Considerations

  • Dirty REF accuracy limited by

reference ripple

– Function of CP/CM vs. CR

  • Clean REF accuracy limited by

comparator noise

– Over-designed for low-noise – Can decimate to save power (only operate once every N cycles)

Slide 37

VDD prepare

CP

VSS prepare

CM

Charge source / sink

CR

VREF_ext

prepare +

replica out

connect connect

slide-39
SLIDE 39

2020 Symposia on VLSI Technology and Circuits CD1.1

Regulator Design Values

  • All capacitors made tunable

for testing purposes

  • Regulator area can be

significantly reduced

– Many non-essential test features

Slide 38

CP CM CR

VCM 130 fF 130 fF 45 pF VREFP_dirty 4pF

  • 45 pF

VREFM_dirty

  • 2 pF

45 pF VREFP_clean 320 fF 24 fF 120 pF VREFM_clean 20 fF 320 fF 120 pF

Nominal Capacitor Values

slide-40
SLIDE 40

2020 Symposia on VLSI Technology and Circuits CD1.1

Outline

  • Ringamp Topology
  • Fully Dynamic Reference Regulation
  • Scope-on-Chip Amplifier Settling Monitor
  • Performance Summary & Conclusion

Slide 39

slide-41
SLIDE 41

2020 Symposia on VLSI Technology and Circuits CD1.1

2 Approaches to Ringamp Robustness

  • Robust by design

– No calibration, but needs design margin – Several SoTA designs using this: [Hung, ISSCC 2020] 100MS/s, 71.7dB SNDR, 2.2fJ/c-step FoMW [Lim, JSSC Dec. 2015] 50MS/s, 70.9dB SNDR, 6.9fJ/c-step FoMW [Lim, VLSI 2017] 100MS/s, 73.2dB SNDR, 6.1fJ/c-step FoMW

  • Robust by background tuning / calibration / digital assistance

– Max performance, but possibly more complex – Less has been tried here - interesting research questions! [Hershberg, ISSCC 2019, Paper 3.1]

Slide 40

slide-42
SLIDE 42

2020 Symposia on VLSI Technology and Circuits CD1.1

Ringamp Waveform Capture

  • Main goals:
  • 1. Background capture of amplifier settling waveform
  • 2. Use this information to optimize ringamp biasing / performance

Slide 41 IN

c circuit of interest monitor circuit T/H

txN

T/H

tend V(tend) V(txN) V(txN)-V(tend)

ADC

Range Detect (sort w.r.t. backend code) demux

D(tx1) D(tx2) D(txN) D(tx1) D(tx2) D(txN)

wave[1]

D(tx1) D(tx2) D(txN)

wave[2] wave[n] reconstructed wave[n]:

digital processing Δ β

ringamp

– +

slide-43
SLIDE 43

2020 Symposia on VLSI Technology and Circuits CD1.1 IN

c circuit of interest monitor circuit T/H

txN

T/H

tend V(tend) V(txN) V(txN)-V(tend)

ADC

Range Detect (sort w.r.t. backend code) demux

D(tx1) D(tx2) D(txN) D(tx1) D(tx2) D(txN)

wave[1]

D(tx1) D(tx2) D(txN)

wave[2] wave[n] reconstructed wave[n]:

digital processing Δ β

ringamp

– +

Ringamp Waveform Monitoring

Challenge 1: Large residue range

Slide 42

slide-44
SLIDE 44

2020 Symposia on VLSI Technology and Circuits CD1.1 IN

c circuit of interest monitor circuit T/H

txN

T/H

tend V(tend) V(txN) V(txN)-V(tend)

ADC

Range Detect (sort w.r.t. backend code) demux

D(tx1) D(tx2) D(txN) D(tx1) D(tx2) D(txN)

wave[1]

D(tx1) D(tx2) D(txN)

wave[2] wave[n] reconstructed wave[n]:

digital processing Δ β

ringamp

– +

Ringamp Waveform Monitoring

Challenge 1: Large residue range Solution: Sample w.r.t. final value

Slide 43

slide-45
SLIDE 45

2020 Symposia on VLSI Technology and Circuits CD1.1 IN

c circuit of interest monitor circuit T/H

txN

T/H

tend V(tend) V(txN) V(txN)-V(tend)

ADC

Range Detect (sort w.r.t. backend code) demux

D(tx1) D(tx2) D(txN) D(tx1) D(tx2) D(txN)

wave[1]

D(tx1) D(tx2) D(txN)

wave[2] wave[n] reconstructed wave[n]:

digital processing Δ β

ringamp

– +

Ringamp Waveform Monitoring

Challenge 2: Time-series capture Solution: Combine cycles with similar V(tend)

Slide 44

V(tend) V(tx1) V(tx2) V(tx3) Sampling instant txN is tunable V(tx4)

slide-46
SLIDE 46

2020 Symposia on VLSI Technology and Circuits CD1.1 IN

c circuit of interest monitor circuit T/H

txN

T/H

tend V(tend) V(txN) V(txN)-V(tend)

ADC

Range Detect (sort w.r.t. backend code) demux

D(tx1) D(tx2) D(txN) D(tx1) D(tx2) D(txN)

wave[1]

D(tx1) D(tx2) D(txN)

wave[2] wave[n] reconstructed wave[n]:

digital processing Δ β

ringamp

– +

Ringamp Waveform Monitoring

Challenge 2: Time-series capture

Slide 45

slide-47
SLIDE 47

2020 Symposia on VLSI Technology and Circuits CD1.1 IN

c circuit of interest monitor circuit T/H

txN

T/H

tend V(tend) V(txN) V(txN)-V(tend)

ADC

Range Detect (sort w.r.t. backend code) demux

D(tx1) D(tx2) D(txN) D(tx1) D(tx2) D(txN)

wave[1]

D(tx1) D(tx2) D(txN)

wave[2] wave[n] reconstructed wave[n]:

digital processing Δ β

ringamp

– +

Ringamp Waveform Monitoring

Challenge 2: Time-series capture Solution: Combine cycles with similar V(tend)

Slide 46 Sort by DC level

slide-48
SLIDE 48

2020 Symposia on VLSI Technology and Circuits CD1.1 IN

c circuit of interest monitor circuit T/H

txN

T/H

tend V(tend) V(txN) V(txN)-V(tend)

ADC

Range Detect (sort w.r.t. backend code) demux

D(tx1) D(tx2) D(txN) D(tx1) D(tx2) D(txN)

wave[1]

D(tx1) D(tx2) D(txN)

wave[2] wave[n] reconstructed wave[n]:

digital processing Δ β

ringamp

– +

Ringamp Waveform Monitoring

Challenge 3: Low complexity

Slide 47

slide-49
SLIDE 49

2020 Symposia on VLSI Technology and Circuits CD1.1 IN

c circuit of interest monitor circuit T/H

txN

T/H

tend V(tend) V(txN) V(txN)-V(tend)

1b ADC

Range Detect (sort w.r.t. backend code) demux

D(tx1) D(tx2) D(txN) D(tx1) D(tx2) D(txN)

wave[1]

D(tx1) D(tx2) D(txN)

wave[2] wave[n] reconstructed wave[n]:

digital processing Δ β

ringamp

– +

Ringamp Waveform Monitoring

Challenge 3: Low complexity Solution: 1-bit stochastic ADC

Slide 48 [Verbruggen, JSSC, Sept. 2015] + VIN

Input-referred noise PDF 1,1,0,1,0,0,1,...

erf -1 avg vREF/σREF

VX avg(1,1,0,1,...) Comparator

  • utput CDF

D(VIN)

erf(σX)

Concept: use a comparator’s gaussian noise distribution to quantize

slide-50
SLIDE 50

2020 Symposia on VLSI Technology and Circuits CD1.1 IN

c circuit of interest monitor circuit T/H

txN

T/H

tend V(tend) V(txN) V(txN)-V(tend)

1b ADC

Range Detect (sort w.r.t. backend code) demux

D(tx1) D(tx2) D(txN) D(tx1) D(tx2) D(txN)

wave[1]

D(tx1) D(tx2) D(txN)

wave[2] wave[n] reconstructed wave[n]:

digital processing Δ β

ringamp

– +

Ringamp Waveform Monitoring

Challenge 3: Low complexity Solution: 1-bit stochastic ADC

Slide 49 [Verbruggen, JSSC, Sept. 2015] + VIN

Input-referred noise PDF 1,1,0,1,0,0,1,...

erf -1 avg vREF/σREF

VX avg(1,1,0,1,...) Comparator

  • utput CDF

D(VIN)

erf(σX)

slide-51
SLIDE 51

2020 Symposia on VLSI Technology and Circuits CD1.1 IN

c circuit of interest monitor circuit T/H

txN

T/H

tend V(tend) V(txN) V(txN)-V(tend)

1b ADC

Range Detect (sort w.r.t. backend code) demux

D(tx1) D(tx2) D(txN) D(tx1) D(tx2) D(txN)

wave[1]

D(tx1) D(tx2) D(txN)

wave[2] wave[n] reconstructed wave[n]:

digital processing Δ β

ringamp

– +

Ringamp Waveform Monitoring

Challenge 3: Low complexity Solution: 1-bit stochastic ADC

Slide 50 + VIN

Input-referred noise PDF 1,1,0,1,0,0,1,...

erf -1 avg vREF/σREF

VX avg(1,1,0,1,...) Comparator

  • utput CDF

D(VIN)

erf(σX)

[Verbruggen, JSSC, Sept. 2015]

If some distortion acceptable, can skip these steps

slide-52
SLIDE 52

2020 Symposia on VLSI Technology and Circuits CD1.1 IN

c circuit of interest monitor circuit T/H

txN

T/H

tend V(tend) V(txN) V(txN)-V(tend)

1b ADC

Range Detect (sort w.r.t. backend code) demux

D(tx1) D(tx2) D(txN) D(tx1) D(tx2) D(txN)

wave[1]

D(tx1) D(tx2) D(txN)

wave[2] wave[n] reconstructed wave[n]:

digital processing Δ β

ringamp

– +

Ringamp Waveform Monitoring

Challenge 3: Low complexity Solution: 1-bit stochastic ADC

Slide 51 + VIN

1,1,0,1,0,0,1,...

avg D(VIN)

slide-53
SLIDE 53

2020 Symposia on VLSI Technology and Circuits CD1.1

Practical Implementation

Slide 52

  • Monitor circuit

added to output of each stage

  • Single-ended

scheme here

– Dummy sampler also on OUTp – Fully differential also possible

Simplified MDAC INp

VCM 1.5b sub-ADC DOUT[1:0] Ringamp +

  • 1.5b

sub-DAC c c c c

INm OUTp OUTm

+

DOUT

controller

tend txN settling monitor scope on chip

c STG1 1.5b CTOT= 256fF STG2 1.5b CTOT= 128fF c

master clock

BACKEND 1.5b + 3b CTOT= 256fF STG3 1.5b CTOT= 128fF STG4 1.5b CTOT= 128fF STG5 1.5b CTOT= 128fF STG6 1.5b CTOT= 128fF STG7 1.5b CTOT= 128fF

INm

c

INp

slide-54
SLIDE 54

2020 Symposia on VLSI Technology and Circuits CD1.1 IN

c circuit of interest monitor circuit T/H

txN

T/H

tend V(tend) V(txN) V(txN)-V(tend)

1b ADC

Range Detect (sort w.r.t. backend code) demux

D(tx1) D(tx2) D(txN) D(tx1) D(tx2) D(txN)

wave[1]

D(tx1) D(tx2) D(txN)

wave[2] wave[n] reconstructed wave[n]:

digital processing Δ β

ringamp

– +

Practical Implementation

Slide 53

+

OUTm disable (sample_final) (sample_early) DOUT V(txN) 1-bit stochastic ADC V(tend) 3fF 3fF (sample_early) (sample_final) compare txN tend

slide-55
SLIDE 55

2020 Symposia on VLSI Technology and Circuits CD1.1 IN

c circuit of interest monitor circuit T/H

txN

T/H

tend V(tend) V(txN) V(txN)-V(tend)

1b ADC

Range Detect (sort w.r.t. backend code) demux

D(tx1) D(tx2) D(txN) D(tx1) D(tx2) D(txN)

wave[1]

D(tx1) D(tx2) D(txN)

wave[2] wave[n] reconstructed wave[n]:

digital processing Δ β

ringamp

– +

Practical Implementation

Slide 54

+

OUTm disable (sample_final) (sample_early) DOUT V(txN) 1-bit stochastic ADC V(tend) 3fF 3fF (sample_early) (sample_final) compare txN tend

Tiny Sampling Capacitance More noise means larger stochastic ADC input range. Here, kT/C is good thing!

slide-56
SLIDE 56

2020 Symposia on VLSI Technology and Circuits CD1.1

OUTp

caps & switches

OUTm

STAGE N STAGE N+1 Comparator & controller

Practical Implementation

Slide 55

+

OUTm disable (sample_final) (sample_early) DOUT V(txN) 1-bit stochastic ADC V(tend) 3fF 3fF (sample_early) (sample_final) compare txN tend G A B = VSS = node V(txN) = node V(tend)

A B G G G G G G G G G G G G G

Capacitors built from routing wires Compact layout between pipeline stages

2µm 7µm

slide-57
SLIDE 57

2020 Symposia on VLSI Technology and Circuits CD1.1

Measured Amplifier Settling Waveforms

  • Provides direct insight into

amplifier settling behavior!

– Verification – Debug – Calibration?...

Slide 56

  • Crit. Damped

Over Damped Unstable Under Damped

slide-58
SLIDE 58

2020 Symposia on VLSI Technology and Circuits CD1.1

Ringamp Waveform Capture

  • Main goals:
  • 1. Background capture of amplifier settling waveform ✓
  • 2. Use this information to optimize ringamp biasing / performance

Slide 57 IN

c circuit of interest monitor circuit T/H

txN

T/H

tend V(tend) V(txN) V(txN)-V(tend)

ADC

Range Detect (sort w.r.t. backend code) demux

D(tx1) D(tx2) D(txN) D(tx1) D(tx2) D(txN)

wave[1]

D(tx1) D(tx2) D(txN)

wave[2] wave[n] reconstructed wave[n]:

digital processing Δ β

ringamp

– +

slide-59
SLIDE 59

2020 Symposia on VLSI Technology and Circuits CD1.1

Defining an Objective Function for Bias Control

  • Observation: only the

Critically Damped case has: – Initial large amplitude – Final small amplitude

  • Estimator = P2 / P1
  • Other variations of

this concept also work

Slide 58

P1 P2 P1 P2 P1 P2

Over Damped (code 150)

  • Crit. Damped

(code 100) Under Damped (code 50)

slide-60
SLIDE 60

2020 Symposia on VLSI Technology and Circuits CD1.1

Defining an Objective Function for Bias Control

  • Estimator = P2 / P1
  • Accurately predicts the bias
  • ptimum (within certain

margin) ✓

  • PVT tracking loop possible

– But not implemented

Slide 59

Critical Damping Estimator (Obj. Fun.)

Best SNDR at code 100

slide-61
SLIDE 61

2020 Symposia on VLSI Technology and Circuits CD1.1

Background operation of Ringamp Monitor

  • Monitor circuit samples

during normal operation

– Disturbs residue slightly

Slide 60

  • Minimal performance impact ✓

– SNDR: no loss – THD: no loss – SFDR:

  • 3dB worst-case
slide-62
SLIDE 62

2020 Symposia on VLSI Technology and Circuits CD1.1

Outline

  • Ringamp Topology
  • Fully Dynamic Reference Regulation
  • Scope-on-Chip Amplifier Settling Monitor
  • Performance Summary & Conclusion

Slide 61

slide-63
SLIDE 63

2020 Symposia on VLSI Technology and Circuits CD1.1

Measurement Results

  • 16nm CMOS FinFET
  • 0.095 mm2

Slide 62

slide-64
SLIDE 64

2020 Symposia on VLSI Technology and Circuits CD1.1

ADC Output Spectrum with Regulation

Slide 63

FIN = 100MHz, FCLK = 1GHz FIN = 500MHz, FCLK = 1GHz

Decimated Frequency NDEC=457 Decimated Frequency NDEC=457 dBFS dBFS

slide-65
SLIDE 65

2020 Symposia on VLSI Technology and Circuits CD1.1

Frequency Sweeps

Slide 64

FCLK Sweep: 1MHz – 1GHz FIN Sweep: 100MHz – 500MHz

slide-66
SLIDE 66

2020 Symposia on VLSI Technology and Circuits CD1.1

Regulator Performance

  • Regulator only 8% of

total ADC power

– Majority of power delivered to load – High efficiency

  • Decimation of clean

regulators improves efficiency

  • Minimal impact on

noise & SNDR

Slide 65

Mode of Operation Mode of Operation

slide-67
SLIDE 67

2020 Symposia on VLSI Technology and Circuits CD1.1

Performance Summary

  • 1GS/s single channel 9.6 ENOB
  • Full dynamic reference regulation
  • FoMW 14fJ/c-step from 1MS/s – 1GS/s

Slide 66

Technology Supply Sampling Rate Resolution Input Range Performance at 1GS/s: 100 MHz input: 500 MHz input: ENOB 9.7 b 9.6 b SNDR 59.8 dB 59.5 dB SFDR 78.6 dB 75.9 dB THD 71.8 dB 69.9 dB Total Power ADC Regulator Walden FoM Schreier FoM Active Area 16nm CMOS 1.6 V pk-pk diff. 0.9 V 1MS/s - 1 GS/s 11b 0.9 mW (8%) 10.9 mW 14.1 fJ/c-step 166.1 dB 0.095 mm2 10.0 mW (92%)

slide-68
SLIDE 68

2020 Symposia on VLSI Technology and Circuits CD1.1

Contributions & Conclusions

  • High-Speed Ringamp Topology

– Elegant operation

  • Fully-Dynamic Discrete-Time Reference Regulation

– Many applications (pipeline, SAR, ...) – Any accuracy / noise requirement

  • Stochastic ADC “Scope-on-Chip”

– Small, simple, high resolution, background operation – Other interesting applications: e.g. supply and reference diagnostics

Slide 67

slide-69
SLIDE 69

2020 Symposia on VLSI Technology and Circuits CD1.1

Thank you for your attention!

Slide 68